From: Imre Deak Date: Wed, 27 Jul 2022 16:45:23 +0000 (+0300) Subject: drm/i915/d13: Add Wa_16015201720 disabling clock gating for PIPEDMC-A/B X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=f31bccd3989d504a0c90b4562908ea18162d7662;p=linux.git drm/i915/d13: Add Wa_16015201720 disabling clock gating for PIPEDMC-A/B Add a workaround making sure that PIPEDMC-A/B is enabled when the firmware needs these on D13 platforms to save/restore the registers backed by the PW_1 and PW_A power wells. Signed-off-by: Imre Deak Reviewed-by: Uma Shankar Link: https://patchwork.freedesktop.org/patch/msgid/20220727164523.1621361-2-imre.deak@intel.com --- diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index 22f65a9968c6a..13aaa3247a5a8 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -1615,6 +1615,14 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv, intel_de_rmw(dev_priv, SOUTH_DSPCLK_GATE_D, 0, PCH_DPMGUNIT_CLOCK_GATE_DISABLE); + /* Wa_16015201720:adl-p,dg2 */ + if (DISPLAY_VER(dev_priv) == 13) { + intel_de_rmw(dev_priv, CLKGATE_DIS_PSL_EXT(PIPE_A), + 0, PIPEDMC_GATING_DIS); + intel_de_rmw(dev_priv, CLKGATE_DIS_PSL_EXT(PIPE_B), + 0, PIPEDMC_GATING_DIS); + } + /* 1. Enable PCH reset handshake. */ intel_pch_reset_handshake(dev_priv, !HAS_PCH_NOP(dev_priv)); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index d38939a775ce8..0d1b0022f4b7b 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1892,6 +1892,13 @@ #define CLKGATE_DIS_PSL(pipe) \ _MMIO_PIPE(pipe, _CLKGATE_DIS_PSL_A, _CLKGATE_DIS_PSL_B) +#define _CLKGATE_DIS_PSL_EXT_A 0x4654C +#define _CLKGATE_DIS_PSL_EXT_B 0x46550 +#define PIPEDMC_GATING_DIS REG_BIT(12) + +#define CLKGATE_DIS_PSL_EXT(pipe) \ + _MMIO_PIPE(pipe, _CLKGATE_DIS_PSL_EXT_A, _CLKGATE_DIS_PSL_EXT_B) + /* * Display engine regs */