From: Richard Henderson <richard.henderson@linaro.org>
Date: Sun, 17 Apr 2022 17:43:29 +0000 (-0700)
Subject: target/arm: Update SCR_EL3 bits to ARMv8.8
X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=f527d66183d8cbd9b2f4cdd428b8b3f685fd9e2a;p=qemu.git

target/arm: Update SCR_EL3 bits to ARMv8.8

Update SCR_EL3 fields per ARM DDI0487 H.a.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 564821eede..cc8f7f74ea 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1545,6 +1545,18 @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
 #define SCR_FIEN              (1U << 21)
 #define SCR_ENSCXT            (1U << 25)
 #define SCR_ATA               (1U << 26)
+#define SCR_FGTEN             (1U << 27)
+#define SCR_ECVEN             (1U << 28)
+#define SCR_TWEDEN            (1U << 29)
+#define SCR_TWEDEL            MAKE_64BIT_MASK(30, 4)
+#define SCR_TME               (1ULL << 34)
+#define SCR_AMVOFFEN          (1ULL << 35)
+#define SCR_ENAS0             (1ULL << 36)
+#define SCR_ADEN              (1ULL << 37)
+#define SCR_HXEN              (1ULL << 38)
+#define SCR_TRNDR             (1ULL << 40)
+#define SCR_ENTP2             (1ULL << 41)
+#define SCR_GPF               (1ULL << 48)
 
 #define HSTR_TTEE (1 << 16)
 #define HSTR_TJDBX (1 << 17)