From: Geert Uytterhoeven <geert+renesas@glider.be>
Date: Wed, 26 Oct 2022 10:37:51 +0000 (+0200)
Subject: Merge tag 'renesas-clk-fixes-for-v6.1-tag1'
X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=f5684bde0375f4feb2a9ed1c146df29437652e70;p=linux.git

Merge tag 'renesas-clk-fixes-for-v6.1-tag1'

clk: renesas: Fixes for v6.1

  - Correct the parent clocks for the High Speed Serial Communication
    Interfaces with FIFO (HSCIF) modules on the R-Car V4H SoC.
    Note that HSCIF0 is used for the serial console on the White-Hawk
    development board.
---

f5684bde0375f4feb2a9ed1c146df29437652e70