From: Fabiano Rosas <farosas@linux.ibm.com>
Date: Wed, 9 Feb 2022 08:08:55 +0000 (+0100)
Subject: target/ppc: booke: Alignment interrupt cleanup
X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=f7a28f711939fe873dee762aa7dfe9f4bb63be06;p=qemu.git

target/ppc: booke: Alignment interrupt cleanup

BookE has no DSISR or DAR. The proper registers ESR and DEAR were
already set at this point.

Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20220128224018.1228062-9-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---

diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 6d86ae04eb..dfcb9995b8 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -844,13 +844,6 @@ static void powerpc_excp_booke(PowerPCCPU *cpu, int excp)
         }
         break;
     case POWERPC_EXCP_ALIGN:     /* Alignment exception                      */
-        /* Get rS/rD and rA from faulting opcode */
-        /*
-         * Note: the opcode fields will not be set properly for a
-         * direct store load/store, but nobody cares as nobody
-         * actually uses direct store segments.
-         */
-        env->spr[SPR_DSISR] |= (env->error_code & 0x03FF0000) >> 16;
         break;
     case POWERPC_EXCP_PROGRAM:   /* Program exception                        */
         switch (env->error_code & ~0xF) {