From: Peter Geis <pgwipeout@gmail.com>
Date: Wed, 28 Jul 2021 18:00:32 +0000 (-0400)
Subject: arm64: dts: rockchip: adjust rk3568 pll clocks
X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=f7c5b9c2a1af765de0aae3a21073e051e95448bf;p=linux.git

arm64: dts: rockchip: adjust rk3568 pll clocks

The rk3568 gpll should run at 1200mhz and the ppll should run at 200mhz.
These are set incorrectly by the bootloader, so fix them here.

gpll boots at 1188mhz, but to get most accurate dividers for all
gpll_dividers it needs to run at 1200mhz, otherwise everyone downstream
isn't quite right.

ppll feeds the combophys, which has a divide by 2 clock, so 200mhz is
required to reach a 100mhz clock input for them.

The vendor-kernel also makes this fix.

Signed-off-by: Peter Geis <pgwipeout@gmail.com>
[pulled deeper explanation from discussion into commit message]
Link: https://lore.kernel.org/r/20210728180034.717953-7-pgwipeout@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---

diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
index 874d8b9776798..bef747fb1fe26 100644
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
@@ -222,6 +222,8 @@
 		reg = <0x0 0xfdd20000 0x0 0x1000>;
 		#clock-cells = <1>;
 		#reset-cells = <1>;
+		assigned-clocks = <&cru PLL_GPLL>, <&pmucru PLL_PPLL>;
+		assigned-clock-rates = <1200000000>, <200000000>;
 	};
 
 	i2c0: i2c@fdd40000 {