From: Jitao Shi Date: Wed, 7 Aug 2019 08:46:43 +0000 (+0800) Subject: dt-bindings: display: mediatek: update dsi supported chips X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=f92013259d32c903d360039ff26a659f8f1552f5;p=linux.git dt-bindings: display: mediatek: update dsi supported chips Update device tree binding documentation for the dsi for Mediatek MT8183 SoCs. Signed-off-by: Jitao Shi Acked-by: Rob Herring Signed-off-by: CK Hu --- diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt index fadf327c7cdf7..a19a6cc375ed7 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt @@ -7,7 +7,7 @@ channel output. Required properties: - compatible: "mediatek,-dsi" - the supported chips are mt2701 and mt8173. + the supported chips are mt2701, mt8173 and mt8183. - reg: Physical base address and length of the controller's registers - interrupts: The interrupt signal from the function block. - clocks: device clocks @@ -26,7 +26,7 @@ The MIPI TX configuration module controls the MIPI D-PHY. Required properties: - compatible: "mediatek,-mipi-tx" - the supported chips are mt2701 and mt8173. + the supported chips are mt2701, mt8173 and mt8183. - reg: Physical base address and length of the controller's registers - clocks: PLL reference clock - clock-output-names: name of the output clock line to the DSI encoder