From: Tony Cheng Date: Thu, 13 Jul 2017 02:00:34 +0000 (-0400) Subject: drm/amd/display: register programming consolidation X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=fc0956909f24d2cd6f69777881bcccd771a06f35;p=linux.git drm/amd/display: register programming consolidation remove redundant DPP_CLOCK_ENABLE in ipp. clock programmed by HWSS Signed-off-by: Tony Cheng Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c index 4910d4c59b310..53dd9a9593f09 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c @@ -418,7 +418,6 @@ static void ippn10_enable_cm_block( { struct dcn10_ipp *ippn10 = TO_DCN10_IPP(ipp); - REG_UPDATE(DPP_CONTROL, DPP_CLOCK_ENABLE, 1); REG_UPDATE(CM_CONTROL, CM_BYPASS_EN, 0); } diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h index 1703589623b02..f14e208dbf1c2 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h @@ -235,7 +235,6 @@ IPP_SF(CM0_CM_DGAM_LUT_WRITE_EN_MASK, CM_DGAM_LUT_WRITE_SEL, mask_sh), \ IPP_SF(CM0_CM_DGAM_LUT_INDEX, CM_DGAM_LUT_INDEX, mask_sh), \ IPP_SF(CM0_CM_DGAM_LUT_DATA, CM_DGAM_LUT_DATA, mask_sh), \ - IPP_SF(DPP_TOP0_DPP_CONTROL, DPP_CLOCK_ENABLE, mask_sh), \ IPP_SF(CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT, CNVC_SURFACE_PIXEL_FORMAT, mask_sh), \ IPP_SF(CNVC_CFG0_FORMAT_CONTROL, CNVC_BYPASS, mask_sh), \ IPP_SF(CNVC_CFG0_FORMAT_CONTROL, ALPHA_EN, mask_sh), \ @@ -433,7 +432,6 @@ type CM_DGAM_LUT_WRITE_SEL; \ type CM_DGAM_LUT_INDEX; \ type CM_DGAM_LUT_DATA; \ - type DPP_CLOCK_ENABLE; \ type CM_BYPASS_EN; \ type CM_BYPASS; \ type CNVC_SURFACE_PIXEL_FORMAT; \