From: Rohit Agarwal Date: Thu, 20 Jul 2023 08:09:03 +0000 (+0530) Subject: arm64: dts: qcom: sm8350: Update the RPMHPD bindings entry X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=fc4cbfbb7fb2ce5ad6c2afa3e529e8f04021d5fc;p=linux.git arm64: dts: qcom: sm8350: Update the RPMHPD bindings entry Update the RPMHPD bindings entry as per the new generic bindings defined in rpmhpd.h for SM8350 SoC. Signed-off-by: Rohit Agarwal Link: https://lore.kernel.org/r/1689840545-5094-3-git-send-email-quic_rohiagar@quicinc.com Signed-off-by: Bjorn Andersson --- diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index b1f9f447b78b5..d34d02aee9192 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -745,7 +746,7 @@ clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; interrupts = ; - power-domains = <&rpmhpd SM8350_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table_120mhz>; dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, <&gpi_dma2 1 0 QCOM_GPI_SPI>; @@ -777,7 +778,7 @@ clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; interrupts = ; - power-domains = <&rpmhpd SM8350_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table_120mhz>; dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, <&gpi_dma2 1 1 QCOM_GPI_SPI>; @@ -809,7 +810,7 @@ clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; interrupts = ; - power-domains = <&rpmhpd SM8350_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, <&gpi_dma2 1 2 QCOM_GPI_SPI>; @@ -841,7 +842,7 @@ clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; interrupts = ; - power-domains = <&rpmhpd SM8350_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, <&gpi_dma2 1 3 QCOM_GPI_SPI>; @@ -859,7 +860,7 @@ clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; interrupts = ; - power-domains = <&rpmhpd SM8350_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, <&gpi_dma2 1 4 QCOM_GPI_SPI>; @@ -877,7 +878,7 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_uart18_default>; interrupts = ; - power-domains = <&rpmhpd SM8350_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; status = "disabled"; }; @@ -904,7 +905,7 @@ clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; interrupts = ; - power-domains = <&rpmhpd SM8350_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, <&gpi_dma2 1 5 QCOM_GPI_SPI>; @@ -971,7 +972,7 @@ clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; interrupts = ; - power-domains = <&rpmhpd SM8350_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, <&gpi_dma0 1 0 QCOM_GPI_SPI>; @@ -1003,7 +1004,7 @@ clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; interrupts = ; - power-domains = <&rpmhpd SM8350_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, <&gpi_dma0 1 1 QCOM_GPI_SPI>; @@ -1035,7 +1036,7 @@ clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; interrupts = ; - power-domains = <&rpmhpd SM8350_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, <&gpi_dma0 1 2 QCOM_GPI_SPI>; @@ -1053,7 +1054,7 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_uart3_default_state>; interrupts = ; - power-domains = <&rpmhpd SM8350_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; status = "disabled"; }; @@ -1066,7 +1067,7 @@ clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; interrupts = ; - power-domains = <&rpmhpd SM8350_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, <&gpi_dma0 1 3 QCOM_GPI_SPI>; @@ -1098,7 +1099,7 @@ clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; interrupts = ; - power-domains = <&rpmhpd SM8350_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, <&gpi_dma0 1 4 QCOM_GPI_SPI>; @@ -1130,7 +1131,7 @@ clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; interrupts = ; - power-domains = <&rpmhpd SM8350_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, <&gpi_dma0 1 5 QCOM_GPI_SPI>; @@ -1162,7 +1163,7 @@ clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; interrupts = ; - power-domains = <&rpmhpd SM8350_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, <&gpi_dma0 1 6 QCOM_GPI_SPI>; @@ -1180,7 +1181,7 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_uart6_default>; interrupts = ; - power-domains = <&rpmhpd SM8350_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; status = "disabled"; }; @@ -1207,7 +1208,7 @@ clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; interrupts = ; - power-domains = <&rpmhpd SM8350_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, <&gpi_dma0 1 7 QCOM_GPI_SPI>; @@ -1274,7 +1275,7 @@ clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; interrupts = ; - power-domains = <&rpmhpd SM8350_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table_120mhz>; dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, <&gpi_dma1 1 0 QCOM_GPI_SPI>; @@ -1306,7 +1307,7 @@ clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; interrupts = ; - power-domains = <&rpmhpd SM8350_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, <&gpi_dma1 1 1 QCOM_GPI_SPI>; @@ -1338,7 +1339,7 @@ clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; interrupts = ; - power-domains = <&rpmhpd SM8350_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, <&gpi_dma1 1 2 QCOM_GPI_SPI>; @@ -1370,7 +1371,7 @@ clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; interrupts = ; - power-domains = <&rpmhpd SM8350_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, <&gpi_dma1 1 3 QCOM_GPI_SPI>; @@ -1402,7 +1403,7 @@ clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; interrupts = ; - power-domains = <&rpmhpd SM8350_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, <&gpi_dma1 1 4 QCOM_GPI_SPI>; @@ -1434,7 +1435,7 @@ clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; interrupts = ; - power-domains = <&rpmhpd SM8350_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, <&gpi_dma1 1 5 QCOM_GPI_SPI>; @@ -2011,8 +2012,8 @@ clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "xo"; - power-domains = <&rpmhpd SM8350_CX>, - <&rpmhpd SM8350_MSS>; + power-domains = <&rpmhpd RPMHPD_CX>, + <&rpmhpd RPMHPD_MSS>; power-domain-names = "cx", "mss"; interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>; @@ -2052,8 +2053,8 @@ clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "xo"; - power-domains = <&rpmhpd SM8350_LCX>, - <&rpmhpd SM8350_LMX>; + power-domains = <&rpmhpd RPMHPD_LCX>, + <&rpmhpd RPMHPD_LMX>; power-domain-names = "lcx", "lmx"; memory-region = <&pil_slpi_mem>; @@ -2122,7 +2123,7 @@ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; interconnect-names = "sdhc-ddr","cpu-sdhc"; iommus = <&apps_smmu 0x4a0 0x0>; - power-domains = <&rpmhpd SM8350_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&sdhc2_opp_table>; bus-width = <4>; dma-coherent; @@ -2483,7 +2484,7 @@ assigned-clock-rates = <19200000>; operating-points-v2 = <&dpu_opp_table>; - power-domains = <&rpmhpd SM8350_MMCX>; + power-domains = <&rpmhpd RPMHPD_MMCX>; interrupt-parent = <&mdss>; interrupts = <0>; @@ -2546,7 +2547,7 @@ #sound-dai-cells = <0>; operating-points-v2 = <&dp_opp_table>; - power-domains = <&rpmhpd SM8350_MMCX>; + power-domains = <&rpmhpd RPMHPD_MMCX>; status = "disabled"; @@ -2614,7 +2615,7 @@ <&mdss_dsi0_phy 1>; operating-points-v2 = <&dsi0_opp_table>; - power-domains = <&rpmhpd SM8350_MMCX>; + power-domains = <&rpmhpd RPMHPD_MMCX>; phys = <&mdss_dsi0_phy>; @@ -2712,7 +2713,7 @@ <&mdss_dsi1_phy 1>; operating-points-v2 = <&dsi1_opp_table>; - power-domains = <&rpmhpd SM8350_MMCX>; + power-domains = <&rpmhpd RPMHPD_MMCX>; phys = <&mdss_dsi1_phy>; @@ -2803,7 +2804,7 @@ #reset-cells = <1>; #power-domain-cells = <1>; - power-domains = <&rpmhpd SM8350_MMCX>; + power-domains = <&rpmhpd RPMHPD_MMCX>; }; pdc: interrupt-controller@b220000 { @@ -3196,8 +3197,8 @@ clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "xo"; - power-domains = <&rpmhpd SM8350_LCX>, - <&rpmhpd SM8350_LMX>; + power-domains = <&rpmhpd RPMHPD_LCX>, + <&rpmhpd RPMHPD_LMX>; power-domain-names = "lcx", "lmx"; memory-region = <&pil_adsp_mem>; @@ -3432,8 +3433,8 @@ clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "xo"; - power-domains = <&rpmhpd SM8350_CX>, - <&rpmhpd SM8350_MXC>; + power-domains = <&rpmhpd RPMHPD_CX>, + <&rpmhpd RPMHPD_MXC>; power-domain-names = "cx", "mxc"; interconnects = <&compute_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>;