From: Nicholas Piggin Date: Thu, 19 May 2022 13:59:05 +0000 (+1000) Subject: target/ppc: Fix eieio memory ordering semantics X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=fcb830af30adaef6219f6b712f24ec3e794cf2c8;p=qemu.git target/ppc: Fix eieio memory ordering semantics The generated eieio memory ordering semantics do not match the instruction definition in the architecture. Add a big comment to explain this strange instruction and correct the memory ordering behaviour. Signed-off: Nicholas Piggin Reviewed-by: Richard Henderson Message-Id: <20220519135908.21282-2-npiggin@gmail.com> Signed-off-by: Daniel Henrique Barboza --- diff --git a/target/ppc/translate.c b/target/ppc/translate.c index fa34f81c30..eb42f7e459 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -3513,7 +3513,32 @@ static void gen_stswx(DisasContext *ctx) /* eieio */ static void gen_eieio(DisasContext *ctx) { - TCGBar bar = TCG_MO_LD_ST; + TCGBar bar = TCG_MO_ALL; + + /* + * eieio has complex semanitcs. It provides memory ordering between + * operations in the set: + * - loads from CI memory. + * - stores to CI memory. + * - stores to WT memory. + * + * It separately also orders memory for operations in the set: + * - stores to cacheble memory. + * + * It also serializes instructions: + * - dcbt and dcbst. + * + * It separately serializes: + * - tlbie and tlbsync. + * + * And separately serializes: + * - slbieg, slbiag, and slbsync. + * + * The end result is that CI memory ordering requires TCG_MO_ALL + * and it is not possible to special-case more relaxed ordering for + * cacheable accesses. TCG_BAR_SC is required to provide this + * serialization. + */ /* * POWER9 has a eieio instruction variant using bit 6 as a hint to