From: Peter Maydell Date: Tue, 6 Feb 2024 13:29:20 +0000 (+0000) Subject: target/arm: The Cortex-R52 has a read-only CBAR X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=fe31d6c72d0046eb633db51dc1d8fb9b231d270f;p=qemu.git target/arm: The Cortex-R52 has a read-only CBAR The Cortex-R52 implements the Configuration Base Address Register (CBAR), as a read-only register. Add ARM_FEATURE_CBAR_RO to this CPU type, so that our implementation provides the register and the associated qdev property. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20240206132931.38376-3-peter.maydell@linaro.org --- diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c index 1125305115..311d654cdc 100644 --- a/target/arm/tcg/cpu32.c +++ b/target/arm/tcg/cpu32.c @@ -809,6 +809,7 @@ static void cortex_r52_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_PMSA); set_feature(&cpu->env, ARM_FEATURE_NEON); set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); + set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); cpu->midr = 0x411fd133; /* r1p3 */ cpu->revidr = 0x00000000; cpu->reset_fpsid = 0x41034023;