From: Peter Chen Date: Wed, 17 May 2023 16:16:43 +0000 (-0400) Subject: phy: cadence: salvo: add bist fix X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=fe5516651e19f1d4d2e239e142e51320e2b2c18c;p=linux.git phy: cadence: salvo: add bist fix Very limited parts may fail to work on full speed mode (both host and device modes) for USB3 port due to higher threshold in full speed receiver of USB2.0 PHY. One example failure symptom is, the enumeration is failed when connecting full speed USB mouse to USB3 port, especially under high temperature. The workaround is to configure threshold voltage value of single ended receiver by setting USB2.0 PHY register AFE_RX_REG5[2:0] to 3'b101. Signed-off-by: Peter Chen Signed-off-by: Frank Li Link: https://lore.kernel.org/r/20230517161646.3418250-4-Frank.Li@nxp.com Signed-off-by: Vinod Koul --- diff --git a/drivers/phy/cadence/phy-cadence-salvo.c b/drivers/phy/cadence/phy-cadence-salvo.c index 2e3d4d8fb8ebf..5633fd21ae7d4 100644 --- a/drivers/phy/cadence/phy-cadence-salvo.c +++ b/drivers/phy/cadence/phy-cadence-salvo.c @@ -91,6 +91,7 @@ /* USB2 PHY register definition */ #define UTMI_REG15 0xaf +#define UTMI_AFE_RX_REG5 0x12 /* TB_ADDR_TX_RCVDETSC_CTRL */ #define RXDET_IN_P3_32KHZ BIT(0) @@ -247,6 +248,7 @@ static int cdns_salvo_phy_init(struct phy *phy) cdns_salvo_write(salvo_phy, USB2_PHY_OFFSET, UTMI_REG15, value | TXVALID_GATE_THRESHOLD_HS_0US); + cdns_salvo_write(salvo_phy, USB2_PHY_OFFSET, UTMI_AFE_RX_REG5, 0x5); udelay(10); clk_disable_unprepare(salvo_phy->clk);