From: Linus Walleij <linus.walleij@linaro.org>
Date: Fri, 11 Jun 2021 13:01:59 +0000 (+0200)
Subject: ARM: dts: ux500: Tag Janice display SPI correct
X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=ffc011b696f0c0e4cd8c991d09a6140e6b866865;p=linux.git

ARM: dts: ux500: Tag Janice display SPI correct

The s6e63m0 display used "type 3" SPI communication so
flag the device as using negative clocking and polarity
on the SPI bus.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---

diff --git a/arch/arm/boot/dts/ste-ux500-samsung-janice.dts b/arch/arm/boot/dts/ste-ux500-samsung-janice.dts
index f14cf316a70a8..825b62146134b 100644
--- a/arch/arm/boot/dts/ste-ux500-samsung-janice.dts
+++ b/arch/arm/boot/dts/ste-ux500-samsung-janice.dts
@@ -266,6 +266,9 @@
 			pinctrl-names = "default";
 			pinctrl-0 = <&panel_default_mode>;
 			spi-3wire;
+			/* TYPE 3: inverse clock polarity and phase */
+			spi-cpha;
+			spi-cpol;
 
 			port {
 				panel_in: endpoint {