Klaus Jensen [Thu, 17 Jun 2021 19:06:51 +0000 (21:06 +0200)]
hw/nvme: remove assert from nvme_get_zone_by_slba
Make nvme_get_zone_by_slba() return NULL if the slba is out of range.
This allows the function to be used without guarding the call with a
call to nvme_check_bounds(), in preparation for the next patch.
Add asserts after calling nvme_get_zone_by_slba() instead.
Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
Reviewed-by: Keith Busch <kbusch@kernel.org>
Klaus Jensen [Thu, 17 Jun 2021 19:06:50 +0000 (21:06 +0200)]
hw/nvme: save reftag when generating pi
Prepare nvme_dif_pract_generate_dif() and nvme_dif_check() to be
callable in smaller increments by making the reftag a pointer parameter
updated by the function.
Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
Reviewed-by: Keith Busch <kbusch@kernel.org>
Klaus Jensen [Thu, 17 Jun 2021 19:06:49 +0000 (21:06 +0200)]
hw/nvme: reimplement dsm to allow cancellation
Prior to this patch, a loop was used to issue multiple "fire and forget"
aios for each range in the command. Without a reference to the aiocb
returned from the blk_aio_pdiscard calls, the aios cannot be canceled.
Fix this by processing the ranges one after another.
As a bonus, this fixes how metadata is cleared (i.e. we only zero it out
if the data was succesfully discarded).
Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
Reviewed-by: Keith Busch <kbusch@kernel.org>
Klaus Jensen [Thu, 17 Jun 2021 19:06:48 +0000 (21:06 +0200)]
hw/nvme: add nvme_block_status_all helper
Pull the gist of nvme_check_dulbe() into a helper function. This is in
preparation for dsm refactoring.
Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
Reviewed-by: Keith Busch <kbusch@kernel.org>
Klaus Jensen [Thu, 17 Jun 2021 19:06:47 +0000 (21:06 +0200)]
hw/nvme: reimplement flush to allow cancellation
Prior to this patch, a broadcast flush would result in submitting
multiple "fire and forget" aios (no reference saved to the aiocbs
returned from the blk_aio_flush calls).
Fix this by issuing the flushes one after another.
Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
Reviewed-by: Keith Busch <kbusch@kernel.org>
Heinrich Schuchardt [Mon, 14 Jun 2021 20:19:01 +0000 (22:19 +0200)]
hw/nvme: default for namespace EUI-64
On machines with version > 6.0 replace a missing EUI-64 by a generated
value.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Klaus Jensen <k.jensen@samsung.com>
Heinrich Schuchardt [Mon, 14 Jun 2021 20:19:00 +0000 (22:19 +0200)]
hw/nvme: namespace parameter for EUI-64
The EUI-64 field is the only identifier for NVMe namespaces in UEFI device
paths. Add a new namespace property "eui64", that provides the user the
option to specify the EUI-64.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Acked-by: Klaus Jensen <k.jensen@samsung.com>
Reviewed-by: Klaus Jensen <k.jensen@samsung.com>
Gollu Appalanaidu [Tue, 27 Apr 2021 06:30:52 +0000 (12:00 +0530)]
hw/nvme: fix csi field for cns 0x00 and 0x11
As per the TP 4056d Namespace types CNS 0x00 and CNS 0x11
CSI field shouldn't use but it is being used for these two
Identify command CNS values, fix that.
Remove 'nvme_csi_has_nvm_support()' helper as suggested by
Klaus we can safely assume NVM command set support for all
namespaces.
Suggested-by: Klaus Jensen <k.jensen@samsung.com>
Signed-off-by: Gollu Appalanaidu <anaidu.gollu@samsung.com>
Reviewed-by: Klaus Jensen <k.jensen@samsung.com>
Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
Niklas Cassel [Fri, 28 May 2021 11:05:07 +0000 (11:05 +0000)]
hw/nvme: add param to control auto zone transitioning to zone state closed
In the Zoned Namespace Command Set Specification, chapter
2.5.1 Managing resources
"The controller may transition zones in the ZSIO:Implicitly Opened state
to the ZSC:Closed state for resource management purposes."
The word may in this sentence means that automatically transitioning
an implicitly opened zone to closed is completely optional.
Add a new parameter so that the user can control if this automatic
transitioning should be performed or not.
Being able to control this can help with verifying that e.g. a user-space
program behaves properly even without this optional ZNS feature.
The default value is set to true, in order to not change the existing
behavior.
Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com>
[k.jensen: moved parameter to controller]
Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
Gollu Appalanaidu [Wed, 21 Apr 2021 12:51:00 +0000 (18:21 +0530)]
hw/nvme: fix lbaf formats initialization
Currently LBAF formats are being intialized based on metadata
size if and only if nvme-ns "ms" parameter is non-zero value.
Since FormatNVM command being supported device parameter "ms"
may not be the criteria to initialize the supported LBAFs.
And make LBAF array as read-only.
Signed-off-by: Gollu Appalanaidu <anaidu.gollu@samsung.com>
Reviewed-by: Klaus Jensen <k.jensen@samsung.com>
Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
Gollu Appalanaidu [Wed, 21 Apr 2021 12:56:46 +0000 (18:26 +0530)]
hw/nvme: add identify namespace flbas/mc enums
Add enums for the Identify Namespace FLBAS and MC fields.
Signed-off-by: Gollu Appalanaidu <anaidu.gollu@samsung.com>
[k.jensen: squashed separate flbas/mc commits into one]
Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
Gollu Appalanaidu [Fri, 21 May 2021 06:08:42 +0000 (11:38 +0530)]
hw/nvme: fix style
Identify command related functions style fix.
Signed-off-by: Gollu Appalanaidu <anaidu.gollu@samsung.com>
Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
Peter Maydell [Mon, 28 Jun 2021 16:08:34 +0000 (17:08 +0100)]
Merge remote-tracking branch 'remotes/vsementsov/tags/pull-jobs-2021-06-25' into staging
block: Make block-copy API thread-safe
# gpg: Signature made Fri 25 Jun 2021 13:40:24 BST
# gpg: using RSA key
8B9C26CDB2FD147C880E86A1561F24C1F19F79FB
# gpg: Good signature from "Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 8B9C 26CD B2FD 147C 880E 86A1 561F 24C1 F19F 79FB
* remotes/vsementsov/tags/pull-jobs-2021-06-25:
block-copy: atomic .cancelled and .finished fields in BlockCopyCallState
block-copy: add CoMutex lock
block-copy: move progress_set_remaining in block_copy_task_end
block-copy: streamline choice of copy_range vs. read/write
block-copy: small refactor in block_copy_task_entry and block_copy_common
co-shared-resource: protect with a mutex
progressmeter: protect with a mutex
blockjob: let ratelimit handle a speed of 0
block-copy: let ratelimit handle a speed of 0
ratelimit: treat zero speed as unlimited
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Peter Maydell [Mon, 28 Jun 2021 13:22:04 +0000 (14:22 +0100)]
Merge remote-tracking branch 'remotes/jsnow-gitlab/tags/floppy-pull-request' into staging
FDC Pull request
# gpg: Signature made Fri 25 Jun 2021 13:54:17 BST
# gpg: using RSA key
F9B7ABDBBCACDF95BE76CBD07DEF8106AAFC390E
# gpg: Good signature from "John Snow (John Huston) <jsnow@redhat.com>" [full]
# Primary key fingerprint: FAEB 9711 A12C F475 812F 18F2 88A9 064D 1835 61EB
# Subkey fingerprint: F9B7 ABDB BCAC DF95 BE76 CBD0 7DEF 8106 AAFC 390E
* remotes/jsnow-gitlab/tags/floppy-pull-request:
hw/block/fdc: Add description to floppy controllers
hw/block/fdc: Extract SysBus floppy controllers to fdc-sysbus.c
hw/block/fdc: Extract ISA floppy controllers to fdc-isa.c
hw/block/fdc: Declare shared prototypes in fdc-internal.h
hw/block/fdc: Replace disabled fprintf() by trace event
hw/isa/Kconfig: Fix missing dependency ISA_SUPERIO -> FDC
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Peter Maydell [Mon, 28 Jun 2021 08:44:41 +0000 (09:44 +0100)]
Merge remote-tracking branch 'remotes/philmd/tags/mips-
20210625' into staging
MIPS patches queue
Various fixes:
- Potential integer overflow (CID
1452921)
- Invalid emulation of nanoMIPS BPOSGE32 opcode
- Missing exception when DINSV opcode used with DSP disabled
- Do not abort but emit exception for invalid BRANCH opcodes
- TCG temporary leaks
Housekeeping:
- Remove dead code / comments
- Restrict few files to TCG, declarations to sysemu
- Merge MSA32 and MSA64 decodetree definitions
# gpg: Signature made Fri 25 Jun 2021 10:22:20 BST
# gpg: using RSA key
FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full]
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE
* remotes/philmd/tags/mips-
20210625:
target/mips: Merge msa32/msa64 decodetree definitions
target/mips: Remove pointless gen_msa()
target/mips: Optimize regnames[] arrays
target/mips: Constify host_to_mips_errno[]
target/mips: fix emulation of nanoMIPS BPOSGE32 instruction
target/mips: Remove microMIPS BPOSGE32 / BPOSGE64 unuseful cases
target/mips: Remove SmartMIPS / MDMX unuseful comments
target/mips: Restrict some system specific declarations to sysemu
target/mips: Move translate.h to tcg/ sub directory
target/mips: Move TCG trace events to tcg/ sub directory
target/mips: Do not abort on invalid instruction
target/mips: Raise exception when DINSV opcode used with DSP disabled
target/mips: Fix more TCG temporary leaks in gen_pool32a5_nanomips_insn
target/mips: Fix TCG temporary leaks in gen_pool32a5_nanomips_insn()
target/mips: Fix potential integer overflow (CID
1452921)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Peter Maydell [Fri, 25 Jun 2021 17:55:58 +0000 (18:55 +0100)]
Merge remote-tracking branch 'remotes/kraxel/tags/audio-
20210624-pull-request' into staging
audio: bugfixes
# gpg: Signature made Thu 24 Jun 2021 13:16:16 BST
# gpg: using RSA key
A0328CFFB93A17A79901FE7D4CB6D8EED3E87138
# gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" [full]
# gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" [full]
# gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" [full]
# Primary key fingerprint: A032 8CFF B93A 17A7 9901 FE7D 4CB6 D8EE D3E8 7138
* remotes/kraxel/tags/audio-
20210624-pull-request:
hw/audio/sb16: Restrict I/O sampling rate range for command 41h/42h
coreaudio: Lock only the buffer
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Peter Maydell [Fri, 25 Jun 2021 16:05:22 +0000 (17:05 +0100)]
Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-
20210624-2' into staging
Third RISC-V PR for 6.1 release
- Fix MISA in the DisasContext
- Fix GDB CSR XML generation
- QOMify the SiFive UART
- Add support for the OpenTitan timer
# gpg: Signature made Thu 24 Jun 2021 13:00:26 BST
# gpg: using RSA key
F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full]
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054
* remotes/alistair/tags/pull-riscv-to-apply-
20210624-2:
hw/riscv: OpenTitan: Connect the mtime and mtimecmp timer
hw/timer: Initial commit of Ibex Timer
hw/char/ibex_uart: Make the register layout private
hw/char: QOMify sifive_uart
hw/char: Consistent function names for sifive_uart
target/riscv: gdbstub: Fix dynamic CSR XML generation
target/riscv: Use target_ulong for the DisasContext misa
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Peter Maydell [Fri, 25 Jun 2021 14:29:07 +0000 (15:29 +0100)]
Merge remote-tracking branch 'remotes/maxreitz/tags/pull-block-2021-06-24' into staging
Block patch:
- Fix Coverity complaint in block/snapshot.c
# gpg: Signature made Thu 24 Jun 2021 12:42:28 BST
# gpg: using RSA key
91BEB60A30DB3E8857D11829F407DB0061D5CF40
# gpg: issuer "mreitz@redhat.com"
# gpg: Good signature from "Max Reitz <mreitz@redhat.com>" [full]
# Primary key fingerprint: 91BE B60A 30DB 3E88 57D1 1829 F407 DB00 61D5 CF40
* remotes/maxreitz/tags/pull-block-2021-06-24:
block/snapshot: Clarify goto fallback behavior
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Philippe Mathieu-Daudé [Mon, 14 Jun 2021 19:32:20 +0000 (21:32 +0200)]
hw/block/fdc: Add description to floppy controllers
Change the '-device help' output from:
Storage devices:
name "floppy", bus floppy-bus, desc "virtual floppy drive"
name "isa-fdc", bus ISA
to:
Storage devices:
name "floppy", bus floppy-bus, desc "virtual floppy drive"
name "isa-fdc", bus ISA, desc "virtual floppy controller"
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id:
20210614193220.
2007159-7-philmd@redhat.com
Signed-off-by: John Snow <jsnow@redhat.com>
Philippe Mathieu-Daudé [Mon, 14 Jun 2021 19:32:19 +0000 (21:32 +0200)]
hw/block/fdc: Extract SysBus floppy controllers to fdc-sysbus.c
Some machines use floppy controllers via the SysBus interface,
and don't need to pull in all the SysBus code.
Extract the SysBus specific code to a new unit: fdc-sysbus.c,
and add a new Kconfig symbol: "FDC_SYSBUS".
Reviewed-by: John Snow <jsnow@redhat.com>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id:
20210614193220.
2007159-6-philmd@redhat.com
Signed-off-by: John Snow <jsnow@redhat.com>
Philippe Mathieu-Daudé [Mon, 14 Jun 2021 19:32:18 +0000 (21:32 +0200)]
hw/block/fdc: Extract ISA floppy controllers to fdc-isa.c
Some machines use floppy controllers via the SysBus interface,
and don't need to pull in all the ISA code.
Extract the ISA specific code to a new unit: fdc-isa.c, and
add a new Kconfig symbol: "FDC_ISA".
This allows us to remove the FIXME from commit
dd0ff8191ab
("isa: express SuperIO dependencies with Kconfig").
Reviewed-by: John Snow <jsnow@redhat.com>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id:
20210614193220.
2007159-5-philmd@redhat.com
Signed-off-by: John Snow <jsnow@redhat.com>
Philippe Mathieu-Daudé [Mon, 14 Jun 2021 19:32:17 +0000 (21:32 +0200)]
hw/block/fdc: Declare shared prototypes in fdc-internal.h
We want to extract ISA/SysBus code from the generic fdc.c file.
First, declare the prototypes we will access from the new units
into a new local header: "fdc-internal.h".
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id:
20210614193220.
2007159-4-philmd@redhat.com
Signed-off-by: John Snow <jsnow@redhat.com>
Philippe Mathieu-Daudé [Mon, 14 Jun 2021 19:32:16 +0000 (21:32 +0200)]
hw/block/fdc: Replace disabled fprintf() by trace event
Reviewed-by: John Snow <jsnow@redhat.com>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id:
20210614193220.
2007159-3-philmd@redhat.com
Signed-off-by: John Snow <jsnow@redhat.com>
Philippe Mathieu-Daudé [Mon, 14 Jun 2021 19:32:15 +0000 (21:32 +0200)]
hw/isa/Kconfig: Fix missing dependency ISA_SUPERIO -> FDC
isa_superio_realize() calls isa_fdc_init_drives(), which is defined
in hw/block/fdc.c, so ISA_SUPERIO needs to select the FDC symbol.
Reported-by: John Snow <jsnow@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id:
20210614193220.
2007159-2-philmd@redhat.com
Fixes: c0ff3795143 ("Introduce a CONFIG_ISA_SUPERIO switch for isa-superio.c")
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: John Snow <jsnow@redhat.com>
Emanuele Giuseppe Esposito [Thu, 24 Jun 2021 07:20:43 +0000 (09:20 +0200)]
block-copy: atomic .cancelled and .finished fields in BlockCopyCallState
By adding acquire/release pairs, we ensure that .ret and .error_is_read
fields are written by block_copy_dirty_clusters before .finished is true,
and that they are read by API user after .finished is true.
The atomic here are necessary because the fields are concurrently modified
in coroutines, and read outside.
Signed-off-by: Emanuele Giuseppe Esposito <eesposit@redhat.com>
Message-Id: <
20210624072043.180494-6-eesposit@redhat.com>
Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com>
Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com>
Emanuele Giuseppe Esposito [Thu, 24 Jun 2021 07:20:42 +0000 (09:20 +0200)]
block-copy: add CoMutex lock
Group various structures fields, to better understand what we need to
protect with a lock and what doesn't need it.
Then, add a CoMutex to protect concurrent access of block-copy
data structures. This mutex also protects .copy_bitmap, because its thread-safe
API does not prevent it from assigning two tasks to the same
bitmap region.
Exceptions to the lock:
- .sleep_state is handled in the series "coroutine: new sleep/wake API"
and thus here left as TODO.
- .finished, .cancelled and reads to .ret and .error_is_read will be
protected in the following patch, because are used also outside
coroutines.
- .skip_unallocated is atomic. Including it under the mutex would
increase the critical sections and make them also much more complex.
We can have it as atomic since it is only written from outside and
read by block-copy coroutines.
Signed-off-by: Emanuele Giuseppe Esposito <eesposit@redhat.com>
Message-Id: <
20210624072043.180494-5-eesposit@redhat.com>
[vsementsov: fix typo in comment]
Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com>
Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com>
Emanuele Giuseppe Esposito [Thu, 24 Jun 2021 07:20:41 +0000 (09:20 +0200)]
block-copy: move progress_set_remaining in block_copy_task_end
Moving this function in task_end ensures to update the progress
anyways, even if there is an error.
It also helps in next patch, allowing task_end to have only
one critical section.
Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com>
Signed-off-by: Emanuele Giuseppe Esposito <eesposit@redhat.com>
Message-Id: <
20210624072043.180494-4-eesposit@redhat.com>
Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com>
Paolo Bonzini [Thu, 24 Jun 2021 07:20:40 +0000 (09:20 +0200)]
block-copy: streamline choice of copy_range vs. read/write
Put the logic to determine the copy size in a separate function, so
that there is a simple state machine for the possible methods of
copying data from one BlockDriverState to the other.
Use .method instead of .copy_range as in-out argument, and
include also .zeroes as an additional copy method.
While at it, store the common computation of block_copy_max_transfer
into a new field of BlockCopyState, and make sure that we always
obey max_transfer; that's more efficient even for the
COPY_RANGE_READ_WRITE case.
Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com>
Signed-off-by: Emanuele Giuseppe Esposito <eesposit@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <
20210624072043.180494-3-eesposit@redhat.com>
Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com>
Emanuele Giuseppe Esposito [Thu, 24 Jun 2021 07:20:39 +0000 (09:20 +0200)]
block-copy: small refactor in block_copy_task_entry and block_copy_common
Use a local variable instead of referencing BlockCopyState through a
BlockCopyCallState or BlockCopyTask every time.
This is in preparation for next patches.
No functional change intended.
Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com>
Signed-off-by: Emanuele Giuseppe Esposito <eesposit@redhat.com>
Message-Id: <
20210624072043.180494-2-eesposit@redhat.com>
Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com>
Emanuele Giuseppe Esposito [Mon, 14 Jun 2021 08:11:30 +0000 (10:11 +0200)]
co-shared-resource: protect with a mutex
co-shared-resource is currently not thread-safe, as also reported
in co-shared-resource.h. Add a QemuMutex because co_try_get_from_shres
can also be invoked from non-coroutine context.
Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com>
Signed-off-by: Emanuele Giuseppe Esposito <eesposit@redhat.com>
Message-Id: <
20210614081130.22134-6-eesposit@redhat.com>
Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com>
Emanuele Giuseppe Esposito [Mon, 14 Jun 2021 08:11:29 +0000 (10:11 +0200)]
progressmeter: protect with a mutex
Progressmeter is protected by the AioContext mutex, which
is taken by the block jobs and their caller (like blockdev).
We would like to remove the dependency of block layer code on the
AioContext mutex, since most drivers and the core I/O code are already
not relying on it.
Create a new C file to implement the ProgressMeter API, but keep the
struct as public, to avoid forcing allocation on the heap.
Also add a mutex to be able to provide an accurate snapshot of the
progress values to the caller.
Signed-off-by: Emanuele Giuseppe Esposito <eesposit@redhat.com>
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Message-Id: <
20210614081130.22134-5-eesposit@redhat.com>
Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com>
Paolo Bonzini [Mon, 14 Jun 2021 08:11:28 +0000 (10:11 +0200)]
blockjob: let ratelimit handle a speed of 0
Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Emanuele Giuseppe Esposito <eesposit@redhat.com>
Message-Id: <
20210614081130.22134-4-eesposit@redhat.com>
Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com>
Paolo Bonzini [Mon, 14 Jun 2021 08:11:27 +0000 (10:11 +0200)]
block-copy: let ratelimit handle a speed of 0
Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Emanuele Giuseppe Esposito <eesposit@redhat.com>
Message-Id: <
20210614081130.22134-3-eesposit@redhat.com>
Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com>
Paolo Bonzini [Mon, 14 Jun 2021 08:11:26 +0000 (10:11 +0200)]
ratelimit: treat zero speed as unlimited
Both users of RateLimit, block-copy.c and blockjob.c, treat
a speed of zero as unlimited, while RateLimit treats it as
"as slow as possible". The latter is nicer from the code
point of view but pretty useless, so disable rate limiting
if a speed of zero is provided.
Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Emanuele Giuseppe Esposito <eesposit@redhat.com>
Message-Id: <
20210614081130.22134-2-eesposit@redhat.com>
Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com>
Peter Maydell [Fri, 25 Jun 2021 11:00:16 +0000 (12:00 +0100)]
Merge remote-tracking branch 'remotes/stsquad/tags/pull-testing-updates-250621-1' into staging
A few miscellaneous fixes
- tweak tcg/kvm based GIC tests
- add header to MTTCG docs
- cleanup checkpatch handling
- GitLab feature and bug request templates
- symbol resolution helper for plugin API
- skip hppa/s390x signals test until fixes arrive
# gpg: Signature made Fri 25 Jun 2021 10:10:57 BST
# gpg: using RSA key
6685AE99E75167BCAFC8DF35FBD0DB095A9E2A44
# gpg: Good signature from "Alex Bennée (Master Work Key) <alex.bennee@linaro.org>" [full]
# Primary key fingerprint: 6685 AE99 E751 67BC AFC8 DF35 FBD0 DB09 5A9E 2A44
* remotes/stsquad/tags/pull-testing-updates-250621-1:
plugins/api: expose symbol lookup to plugins
tests/tcg: skip the signals test for hppa/s390x for now
GitLab: Add "Feature Request" issue template.
GitLab: Add "Bug" issue reporting template
scripts/checkpatch: roll diff tweaking into checkpatch itself
docs/devel: Add a single top-level header to MTTCG's doc
tests/acceptance: tweak the tcg/kvm tests for virt
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Alex Bennée [Wed, 23 Jun 2021 10:27:48 +0000 (11:27 +0100)]
plugins/api: expose symbol lookup to plugins
This is a quality of life helper for plugins so they don't need to
re-implement symbol lookup when dumping an address. The strings are
constant so don't need to be duplicated. One minor tweak is to return
NULL instead of a zero length string to show lookup failed.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Mahmoud Mandour <ma.mandourr@gmail.com>
Message-Id: <
20210608040532.56449-2-ma.mandourr@gmail.com>
Message-Id: <
20210623102749.25686-8-alex.bennee@linaro.org>
Alex Bennée [Wed, 23 Jun 2021 10:27:47 +0000 (11:27 +0100)]
tests/tcg: skip the signals test for hppa/s390x for now
There are fixes currently in flight but as this is getting in the way
of a green CI we might as well skip for now. For reference the fix
series are:
linux-user: Move signal trampolines to new page
20210616011209.
1446045-1-richard.henderson@linaro.org
and
linux-user: Load a vdso for x86_64 and hppa
20210619034329.532318-1-richard.henderson@linaro.org
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Acked-by: Cornelia Huck <cohuck@redhat.com>
Cc: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20210623102749.25686-7-alex.bennee@linaro.org>
John Snow [Wed, 23 Jun 2021 10:27:46 +0000 (11:27 +0100)]
GitLab: Add "Feature Request" issue template.
Based on Peter Krempa's libvirt template, feature.md.
Signed-off-by: John Snow <jsnow@redhat.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
CC: Peter Krempa <pkrempa@redhat.com>
Message-Id: <
20210607153155.
1760158-3-jsnow@redhat.com>
Message-Id: <
20210623102749.25686-6-alex.bennee@linaro.org>
John Snow [Wed, 23 Jun 2021 10:27:45 +0000 (11:27 +0100)]
GitLab: Add "Bug" issue reporting template
Based loosely on libvirt's template, written by Peter Krempa.
Signed-off-by: John Snow <jsnow@redhat.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
CC: Peter Krempa <pkrempa@redhat.com>
Message-Id: <
20210607153155.
1760158-2-jsnow@redhat.com>
Message-Id: <
20210623102749.25686-5-alex.bennee@linaro.org>
Alex Bennée [Wed, 23 Jun 2021 10:27:44 +0000 (11:27 +0100)]
scripts/checkpatch: roll diff tweaking into checkpatch itself
Rather than relying on external tweaks lets just do it inside
checkpatch's direct commitish handling which is QEMU specific code
anyway.
Suggested-by: Daniel P. Berrangé <berrange@redhat.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Reviewed-by: Willian Rampazzo <willianr@redhat.com>
Reviewed-by: Wainer dos Santos Moschetta <wainersm@redhat.com>
Message-Id: <
20210623102749.25686-4-alex.bennee@linaro.org>
Luis Pires [Wed, 23 Jun 2021 10:27:43 +0000 (11:27 +0100)]
docs/devel: Add a single top-level header to MTTCG's doc
Without a single top-level header in the .rst file, the index ended
up linking to all of the top-level headers separately. Now the index
links to the top-level header at the beginning of the document and
any inner headers are correctly linked as sub-items in the index.
Signed-off-by: Luis Pires <luis.pires@eldorado.org.br>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <
20210528123526.144065-1-luis.pires@eldorado.org.br>
Message-Id: <
20210623102749.25686-3-alex.bennee@linaro.org>
Alex Bennée [Wed, 23 Jun 2021 10:27:42 +0000 (11:27 +0100)]
tests/acceptance: tweak the tcg/kvm tests for virt
Really it's only TCG that can select which GIC model you want, KVM
guests should always be using the "host" version of the GIC for which
QEMU already provides a handy shortcut. Make the KVM test use this and
split the TCG test into it's two versions.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Willian Rampazzo <willianr@redhat.com>
Message-Id: <
20210623102749.25686-2-alex.bennee@linaro.org>
Peter Maydell [Fri, 25 Jun 2021 08:10:37 +0000 (09:10 +0100)]
Merge remote-tracking branch 'remotes/kraxel/tags/ui-
20210624-pull-request' into staging
ui: better cocoa integration (ui info + clipboard).
ui: add lang1+lang2 keys, fixes, doc updates.
# gpg: Signature made Thu 24 Jun 2021 09:32:36 BST
# gpg: using RSA key
A0328CFFB93A17A79901FE7D4CB6D8EED3E87138
# gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" [full]
# gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" [full]
# gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" [full]
# Primary key fingerprint: A032 8CFF B93A 17A7 9901 FE7D 4CB6 D8EE D3E8 7138
* remotes/kraxel/tags/ui-
20210624-pull-request:
ui: Make the DisplayType enum entries conditional
Add display suboptions to man pages
input: Add lang1 and lang2 to QKeyCode
ui/cocoa: Add clipboard support
ui/cocoa: Set UI information
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Philippe Mathieu-Daudé [Sat, 29 May 2021 18:06:13 +0000 (20:06 +0200)]
target/mips: Merge msa32/msa64 decodetree definitions
We don't need to maintain 2 sets of decodetree definitions.
Merge them into a single file.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20210617174636.
2902654-3-f4bug@amsat.org>
Philippe Mathieu-Daudé [Sat, 29 May 2021 18:12:16 +0000 (20:12 +0200)]
target/mips: Remove pointless gen_msa()
Only trans_MSA() calls gen_msa(), inline it to simplify.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20210617174636.
2902654-2-f4bug@amsat.org>
Philippe Mathieu-Daudé [Sat, 29 May 2021 18:13:44 +0000 (20:13 +0200)]
target/mips: Optimize regnames[] arrays
Since all entries are no more than 3/4/6 bytes (including nul
terminator), can save space and pie runtime relocations by
declaring regnames[] as array of 3/4/6 const char.
Inspired-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20210617174323.
2900831-10-f4bug@amsat.org>
Philippe Mathieu-Daudé [Tue, 11 May 2021 10:18:06 +0000 (12:18 +0200)]
target/mips: Constify host_to_mips_errno[]
Keep host_to_mips_errno[] in .rodata by marking the array const.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20210617174323.
2900831-9-f4bug@amsat.org>
Aleksandar Rikalo [Tue, 15 Jun 2021 17:22:35 +0000 (17:22 +0000)]
target/mips: fix emulation of nanoMIPS BPOSGE32 instruction
Per the "MIPS® Architecture Extension: nanoMIPS32 DSP Technical
Reference Manual — Revision 0.04" p. 88 "BPOSGE32C", offset argument (imm)
should be left-shifted first.
This change was tested against test_dsp_r1_bposge32.c DSP test.
Reported-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>
Signed-off-by: Filip Vidojevic <filip.vidojevic@syrmia.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <VI1PR0302MB34869449EE56F226FC3C21129C309@VI1PR0302MB3486.eurprd03.prod.outlook.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Philippe Mathieu-Daudé [Sat, 29 May 2021 14:55:07 +0000 (16:55 +0200)]
target/mips: Remove microMIPS BPOSGE32 / BPOSGE64 unuseful cases
These switch cases for the microMIPS BPOSGE32 / BPOSGE64 opcodes have
been added commit
3c824109da0 ("target-mips: microMIPS ASE support").
More than 11 years later it is safe to assume there won't be added
soon. The cases fall back to the default which generates a RESERVED
INSTRUCTION, so it is safe to remove them.
Functionally speaking, the patch is a no-op.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20210617174323.
2900831-8-f4bug@amsat.org>
Philippe Mathieu-Daudé [Sat, 29 May 2021 22:32:16 +0000 (00:32 +0200)]
target/mips: Remove SmartMIPS / MDMX unuseful comments
These placeholder comments for SmartMIPS and MDMX extensions have
been added commit
3c824109da0 ("target-mips: microMIPS ASE support").
More than 11 years later it is safe to assume there won't be added
soon, so remove these unuseful comments.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20210617174323.
2900831-7-f4bug@amsat.org>
Philippe Mathieu-Daudé [Mon, 24 May 2021 12:28:08 +0000 (14:28 +0200)]
target/mips: Restrict some system specific declarations to sysemu
Commit
043715d1e0f ("target/mips: Update ITU to utilize SAARI
and SAAR CP0 registers") declared itc_reconfigure() in public
namespace, while it is restricted to system emulation.
Similarly commit
5679479b9a1 ("target/mips: Move CP0 helpers
to sysemu/cp0.c") restricted cpu_mips_soft_irq() definition to
system emulation, but forgot to restrict its declaration.
To avoid polluting user-mode emulation with these declarations,
restrict them to sysemu. Also restrict the sysemu ITU/ITC/IRQ
fields from CPUMIPSState.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20210617174323.
2900831-6-f4bug@amsat.org>
Philippe Mathieu-Daudé [Mon, 24 May 2021 07:32:16 +0000 (09:32 +0200)]
target/mips: Move translate.h to tcg/ sub directory
We moved various TCG source files in commit
a2b0a27d33e
("target/mips: Move TCG source files under tcg/ sub directory")
but forgot to move the header declaring their prototypes.
Do it now, since all it declares is TCG specific.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20210617174323.
2900831-5-f4bug@amsat.org>
Philippe Mathieu-Daudé [Sun, 30 May 2021 07:02:16 +0000 (09:02 +0200)]
target/mips: Move TCG trace events to tcg/ sub directory
Commit
a2b0a27d33e ("target/mips: Move TCG source files under
tcg/ sub directory") forgot to move the trace-event file.
As it only contains TCG events, move it for consistency.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20210617174323.
2900831-4-f4bug@amsat.org>
Philippe Mathieu-Daudé [Sat, 22 May 2021 18:16:15 +0000 (20:16 +0200)]
target/mips: Do not abort on invalid instruction
On real hardware an invalid instruction doesn't halt the world,
but usually triggers a RESERVED INSTRUCTION exception.
TCG guest code shouldn't abort QEMU anyway.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20210617174323.
2900831-2-f4bug@amsat.org>
Philippe Mathieu-Daudé [Sat, 29 May 2021 16:08:19 +0000 (18:08 +0200)]
target/mips: Raise exception when DINSV opcode used with DSP disabled
Per the "MIPS® DSP Module for MIPS64 Architecture" manual, rev. 3.02,
Table 5.3 "SPECIAL3 Encoding of Function Field for DSP Module":
If the Module/ASE is not implemented, executing such an instruction
must cause a Reserved Instruction Exception.
The DINSV instruction lists the following exceptions:
- Reserved Instruction
- DSP Disabled
If the MIPS core doesn't support the DSP module, or the DSP is
disabled, do not handle the '$rt = $0' case as a no-op but raise
the proper exception instead.
Cc: Jia Liu <proljc@gmail.com>
Fixes: 1cb6686cf92 ("target-mips: Add ASE DSP bit/manipulation instructions")
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20210529165443.
1114402-1-f4bug@amsat.org>
Philippe Mathieu-Daudé [Thu, 17 Jun 2021 16:03:34 +0000 (18:03 +0200)]
target/mips: Fix more TCG temporary leaks in gen_pool32a5_nanomips_insn
Fix multiple TCG temporary leaks in gen_pool32a5_nanomips_insn().
Fixes: 3285a3e4445 ("target/mips: Add emulation of DSP ASE for nanoMIPS - part 1")
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20210617174323.
2900831-3-f4bug@amsat.org>
Philippe Mathieu-Daudé [Sun, 30 May 2021 09:36:29 +0000 (11:36 +0200)]
target/mips: Fix TCG temporary leaks in gen_pool32a5_nanomips_insn()
Fix a pair of TCG temporary leak when translating nanoMIPS SHILO opcode.
Fixes: 3285a3e4445 ("target/mips: Add emulation of DSP ASE for nanoMIPS")
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20210530094538.
1275329-1-f4bug@amsat.org>
Philippe Mathieu-Daudé [Wed, 5 May 2021 21:38:36 +0000 (23:38 +0200)]
target/mips: Fix potential integer overflow (CID
1452921)
Use the BIT_ULL() macro to ensure we use 64-bit arithmetic.
This fixes the following Coverity issue (OVERFLOW_BEFORE_WIDEN):
CID
1452921: Integer handling issues:
Potentially overflowing expression "1 << w" with type "int"
(32 bits, signed) is evaluated using 32-bit arithmetic, and
then used in a context that expects an expression of type
"uint64_t" (64 bits, unsigned).
Fixes: 074cfcb4dae ("target/mips: Implement hardware page table walker")
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20210505215119.
1517465-1-f4bug@amsat.org>
Peter Maydell [Thu, 24 Jun 2021 14:00:33 +0000 (15:00 +0100)]
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-
20210624' into staging
target-arm queue:
* Don't require 'virt' board to be compiled in for ACPI GHES code
* docs: Document which architecture extensions we emulate
* Fix bugs in M-profile FPCXT_NS accesses
* First slice of MVE patches
* Implement MTE3
* docs/system: arm: Add nRF boards description
# gpg: Signature made Thu 24 Jun 2021 14:59:16 BST
# gpg: using RSA key
E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* remotes/pmaydell/tags/pull-target-arm-
20210624: (57 commits)
docs/system: arm: Add nRF boards description
target/arm: Implement MTE3
target/arm: Make VMOV scalar <-> gpreg beatwise for MVE
target/arm: Implement MVE VADDV
target/arm: Implement MVE VHCADD
target/arm: Implement MVE VCADD
target/arm: Implement MVE VADC, VSBC
target/arm: Implement MVE VRHADD
target/arm: Implement MVE VQDMULL (vector)
target/arm: Implement MVE VQDMLSDH and VQRDMLSDH
target/arm: Implement MVE VQDMLADH and VQRDMLADH
target/arm: Implement MVE VRSHL
target/arm: Implement MVE VSHL insn
target/arm: Implement MVE VQRSHL
target/arm: Implement MVE VQSHL (vector)
target/arm: Implement MVE VQADD, VQSUB (vector)
target/arm: Implement MVE VQDMULH, VQRDMULH (vector)
target/arm: Implement MVE VQDMULL scalar
target/arm: Implement MVE VQDMULH and VQRDMULH (scalar)
target/arm: Implement MVE VQADD and VQSUB
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Alexandre Iooss [Mon, 21 Jun 2021 07:56:25 +0000 (09:56 +0200)]
docs/system: arm: Add nRF boards description
This adds the target guide for BBC Micro:bit.
Information is taken from https://wiki.qemu.org/Features/MicroBit
and from hw/arm/nrf51_soc.c.
Signed-off-by: Alexandre Iooss <erdnaxe@crans.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Message-id:
20210621075625.540471-1-erdnaxe@crans.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Peter Collingbourne [Wed, 16 Jun 2021 19:56:14 +0000 (12:56 -0700)]
target/arm: Implement MTE3
MTE3 introduces an asymmetric tag checking mode, in which loads are
checked synchronously and stores are checked asynchronously. Add
support for it.
Signed-off-by: Peter Collingbourne <pcc@google.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20210616195614.11785-1-pcc@google.com
[PMM: Add line to emulation.rst]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Peter Maydell [Thu, 17 Jun 2021 12:16:28 +0000 (13:16 +0100)]
target/arm: Make VMOV scalar <-> gpreg beatwise for MVE
In a CPU with MVE, the VMOV (vector lane to general-purpose register)
and VMOV (general-purpose register to vector lane) insns are not
predicated, but they are subject to beatwise execution if they
are not in an IT block.
Since our implementation always executes all 4 beats in one tick,
this means only that we need to handle PSR.ECI:
* we must do the usual check for bad ECI state
* we must advance ECI state if the insn succeeds
* if ECI says we should not be executing the beat corresponding
to the lane of the vector register being accessed then we
should skip performing the move
Note that if PSR.ECI is non-zero then we cannot be in an IT block.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20210617121628.20116-45-peter.maydell@linaro.org
Peter Maydell [Thu, 17 Jun 2021 12:16:27 +0000 (13:16 +0100)]
target/arm: Implement MVE VADDV
Implement the MVE VADDV insn, which performs an addition
across vector lanes.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20210617121628.20116-44-peter.maydell@linaro.org
Peter Maydell [Thu, 17 Jun 2021 12:16:26 +0000 (13:16 +0100)]
target/arm: Implement MVE VHCADD
Implement the MVE VHCADD insn, which is similar to VCADD
but performs a halving step. This one overlaps with VADC.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20210617121628.20116-43-peter.maydell@linaro.org
Peter Maydell [Thu, 17 Jun 2021 12:16:25 +0000 (13:16 +0100)]
target/arm: Implement MVE VCADD
Implement the MVE VCADD insn, which performs a complex add with
rotate. Note that the size=0b11 encoding is VSBC.
The architecture grants some leeway for the "destination and Vm
source overlap" case for the size MO_32 case, but we choose not to
make use of it, instead always calculating all 16 bytes worth of
results before setting the destination register.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20210617121628.20116-42-peter.maydell@linaro.org
Peter Maydell [Thu, 17 Jun 2021 12:16:24 +0000 (13:16 +0100)]
target/arm: Implement MVE VADC, VSBC
Implement the MVE VADC and VSBC insns. These perform an
add-with-carry or subtract-with-carry of the 32-bit elements in each
lane of the input vectors, where the carry-out of each add is the
carry-in of the next. The initial carry input is either 1 or is from
FPSCR.C; the carry out at the end is written back to FPSCR.C.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20210617121628.20116-41-peter.maydell@linaro.org
Peter Maydell [Thu, 17 Jun 2021 12:16:23 +0000 (13:16 +0100)]
target/arm: Implement MVE VRHADD
Implement the MVE VRHADD insn, which performs a rounded halving
addition.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20210617121628.20116-40-peter.maydell@linaro.org
Peter Maydell [Thu, 17 Jun 2021 12:16:22 +0000 (13:16 +0100)]
target/arm: Implement MVE VQDMULL (vector)
Implement the vector form of the MVE VQDMULL insn.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20210617121628.20116-39-peter.maydell@linaro.org
Peter Maydell [Thu, 17 Jun 2021 12:16:21 +0000 (13:16 +0100)]
target/arm: Implement MVE VQDMLSDH and VQRDMLSDH
Implement the MVE VQDMLSDH and VQRDMLSDH insns, which are
like VQDMLADH and VQRDMLADH except that products are subtracted
rather than added.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20210617121628.20116-38-peter.maydell@linaro.org
Peter Maydell [Thu, 17 Jun 2021 12:16:20 +0000 (13:16 +0100)]
target/arm: Implement MVE VQDMLADH and VQRDMLADH
Implement the MVE VQDMLADH and VQRDMLADH insns. These multiply
elements, and then add pairs of products, double, possibly round,
saturate and return the high half of the result.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20210617121628.20116-37-peter.maydell@linaro.org
Peter Maydell [Thu, 17 Jun 2021 12:16:19 +0000 (13:16 +0100)]
target/arm: Implement MVE VRSHL
Implement the MVE VRSHL insn (vector form).
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20210617121628.20116-36-peter.maydell@linaro.org
Peter Maydell [Thu, 17 Jun 2021 12:16:18 +0000 (13:16 +0100)]
target/arm: Implement MVE VSHL insn
Implement the MVE VSHL insn (vector form).
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20210617121628.20116-35-peter.maydell@linaro.org
Peter Maydell [Thu, 17 Jun 2021 12:16:17 +0000 (13:16 +0100)]
target/arm: Implement MVE VQRSHL
Implement the MV VQRSHL (vector) insn. Again, the code to perform
the actual shifts is borrowed from neon_helper.c.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20210617121628.20116-34-peter.maydell@linaro.org
Peter Maydell [Thu, 17 Jun 2021 12:16:16 +0000 (13:16 +0100)]
target/arm: Implement MVE VQSHL (vector)
Implement the MVE VQSHL insn (encoding T4, which is the
vector-shift-by-vector version).
The DO_SQSHL_OP and DO_UQSHL_OP macros here are derived from
the neon_helper.c code for qshl_u{8,16,32} and qshl_s{8,16,32}.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20210617121628.20116-33-peter.maydell@linaro.org
Peter Maydell [Thu, 17 Jun 2021 12:16:15 +0000 (13:16 +0100)]
target/arm: Implement MVE VQADD, VQSUB (vector)
Implement the vector forms of the MVE VQADD and VQSUB insns.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20210617121628.20116-32-peter.maydell@linaro.org
Peter Maydell [Thu, 17 Jun 2021 12:16:14 +0000 (13:16 +0100)]
target/arm: Implement MVE VQDMULH, VQRDMULH (vector)
Implement the vector forms of the MVE VQDMULH and VQRDMULH insns.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20210617121628.20116-31-peter.maydell@linaro.org
Peter Maydell [Thu, 17 Jun 2021 12:16:13 +0000 (13:16 +0100)]
target/arm: Implement MVE VQDMULL scalar
Implement the MVE VQDMULL scalar insn. This multiplies the top or
bottom half of each element by the scalar, doubles and saturates
to a double-width result.
Note that this encoding overlaps with VQADD and VQSUB; it uses
what in VQADD and VQSUB would be the 'size=0b11' encoding.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20210617121628.20116-30-peter.maydell@linaro.org
Peter Maydell [Thu, 17 Jun 2021 12:16:12 +0000 (13:16 +0100)]
target/arm: Implement MVE VQDMULH and VQRDMULH (scalar)
Implement the MVE VQDMULH and VQRDMULH scalar insns, which multiply
elements by the scalar, double, possibly round, take the high half
and saturate.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20210617121628.20116-29-peter.maydell@linaro.org
Peter Maydell [Thu, 17 Jun 2021 12:16:11 +0000 (13:16 +0100)]
target/arm: Implement MVE VQADD and VQSUB
Implement the MVE VQADD and VQSUB insns, which perform saturating
addition of a scalar to each element. Note that individual bytes of
each result element are used or discarded according to the predicate
mask, but FPSCR.QC is only set if the predicate mask for the lowest
byte of the element is set.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20210617121628.20116-28-peter.maydell@linaro.org
Peter Maydell [Thu, 17 Jun 2021 12:16:10 +0000 (13:16 +0100)]
target/arm: Implement MVE VPST
Implement the MVE VPST insn, which sets the predicate mask
fields in the VPR to the immediate value encoded in the insn.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20210617121628.20116-27-peter.maydell@linaro.org
Peter Maydell [Thu, 17 Jun 2021 12:16:09 +0000 (13:16 +0100)]
target/arm: Implement MVE VBRSR
Implement the MVE VBRSR insn, which reverses a specified
number of bits in each element, setting the rest to zero.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20210617121628.20116-26-peter.maydell@linaro.org
Peter Maydell [Thu, 17 Jun 2021 12:16:08 +0000 (13:16 +0100)]
target/arm: Implement MVE VHADD, VHSUB (scalar)
Implement the scalar variants of the MVE VHADD and VHSUB insns.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20210617121628.20116-25-peter.maydell@linaro.org
Peter Maydell [Thu, 17 Jun 2021 12:16:07 +0000 (13:16 +0100)]
target/arm: Implement MVE VSUB, VMUL (scalar)
Implement the scalar forms of the MVE VSUB and VMUL insns.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20210617121628.20116-24-peter.maydell@linaro.org
Peter Maydell [Thu, 17 Jun 2021 12:16:06 +0000 (13:16 +0100)]
target/arm: Implement MVE VADD (scalar)
Implement the scalar form of the MVE VADD insn. This takes the
scalar operand from a general purpose register.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20210617121628.20116-23-peter.maydell@linaro.org
Alistair Francis [Fri, 18 Jun 2021 07:28:01 +0000 (17:28 +1000)]
hw/riscv: OpenTitan: Connect the mtime and mtimecmp timer
Connect the Ibex timer to the OpenTitan machine. The timer can trigger
the RISC-V MIE interrupt as well as a custom device interrupt.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id:
5e7f4e9b4537f863bcb8db1264b840b56ef2a929.
1624001156.git.alistair.francis@wdc.com
Alistair Francis [Fri, 18 Jun 2021 07:27:54 +0000 (17:27 +1000)]
hw/timer: Initial commit of Ibex Timer
Add support for the Ibex timer. This is used with the RISC-V
mtime/mtimecmp similar to the SiFive CLINT.
We currently don't support changing the prescale or the timervalue.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id:
716fdea2244515ce86a2c46fe69467d013c03147.
1624001156.git.alistair.francis@wdc.com
Alistair Francis [Fri, 18 Jun 2021 07:27:48 +0000 (17:27 +1000)]
hw/char/ibex_uart: Make the register layout private
We don't need to expose the register layout in the public header, so
don't.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id:
c437f570b2b30ab4170387a3ba2fad7d116a4986.
1624001156.git.alistair.francis@wdc.com
Lukas Jünger [Wed, 16 Jun 2021 09:23:26 +0000 (11:23 +0200)]
hw/char: QOMify sifive_uart
This QOMifies the SiFive UART model. Migration and reset have been
implemented.
Signed-off-by: Lukas Jünger <lukas.juenger@greensocs.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id:
20210616092326.59639-3-lukas.juenger@greensocs.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Lukas Jünger [Wed, 16 Jun 2021 09:23:25 +0000 (11:23 +0200)]
hw/char: Consistent function names for sifive_uart
This cleans up function names in the SiFive UART model.
Signed-off-by: Lukas Jünger <lukas.juenger@greensocs.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id:
20210616092326.59639-2-lukas.juenger@greensocs.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Bin Meng [Tue, 15 Jun 2021 08:51:33 +0000 (16:51 +0800)]
target/riscv: gdbstub: Fix dynamic CSR XML generation
Since commit
605def6eeee5 ("target/riscv: Use the RISCVException enum for CSR operations")
the CSR predicate() function was changed to return RISCV_EXCP_NONE
instead of 0 for a valid CSR, but it forgot to update the dynamic
CSR XML generation codes in gdbstub.
Fixes: 605def6eeee5 ("target/riscv: Use the RISCVException enum for CSR operations")
Reported-by: Xuzhou Cheng <xuzhou.cheng@windriver.com>
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Xuzhou Cheng <xuzhou.cheng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id:
20210615085133.389887-1-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Alistair Francis [Mon, 31 May 2021 04:27:14 +0000 (14:27 +1000)]
target/riscv: Use target_ulong for the DisasContext misa
The is_32bit() check in translate.c expects a 64-bit guest to have a
64-bit misa value otherwise the macro check won't work. This patches
fixes that and fixes a Coverity issue at the same time.
Fixes: CID 1453107
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id:
c00176c7518c2a7b4de3eec320b6a683ab56f705.
1622435221.git.alistair.francis@wdc.com
Qiang Liu [Thu, 24 Jun 2021 02:44:47 +0000 (10:44 +0800)]
hw/audio/sb16: Restrict I/O sampling rate range for command 41h/42h
The I/O sampling rate range is enforced to 5000 to 45000HZ according to
commit
a2cd86a9. Setting I/O sampling rate with command 41h/42h, a guest
user can break this assumption and trigger an assertion in audio_calloc
via command 0xd4. This patch restricts the I/O sampling rate range for
command 41h/42h.
Fixes: 85571bc7415 ("audio merge (malc)")
Signed-off-by: Qiang Liu <cyruscyliu@gmail.com>
Message-Id: <
1624502687-5214-1-git-send-email-cyruscyliu@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Peter Maydell [Thu, 24 Jun 2021 08:31:26 +0000 (09:31 +0100)]
Merge remote-tracking branch 'remotes/thuth-gitlab/tags/pull-request-2021-06-21' into staging
* Documentation updates
* Remove leading underscores from header guards
* Display hexadecimal value with '0x' prefix
# gpg: Signature made Mon 21 Jun 2021 11:33:53 BST
# gpg: using RSA key
27B88847EEE0250118F3EAB92ED9D774FE702DB5
# gpg: issuer "thuth@redhat.com"
# gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full]
# gpg: aka "Thomas Huth <thuth@redhat.com>" [full]
# gpg: aka "Thomas Huth <huth@tuxfamily.org>" [full]
# gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown]
# Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5
* remotes/thuth-gitlab/tags/pull-request-2021-06-21:
MAINTAINERS: Add qtest/arm-cpu-features.c to ARM TCG CPUs section
fuzz: Display hexadecimal value with '0x' prefix
Remove leading underscores from QEMU defines
Update documentation to refer to new location for issues
docs/tools/virtiofsd: Fix bad rst syntax
docs/tools/virtiofsd.rst: Do not hard-code the QEMU binary name
docs/interop/live-block-operations: Do not hard-code the QEMU binary name
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Max Reitz [Mon, 3 May 2021 09:54:18 +0000 (02:54 -0700)]
block/snapshot: Clarify goto fallback behavior
In the bdrv_snapshot_goto() fallback code, we work with a pointer to
either bs->file or bs->backing. We detach that child, close the node
(with .bdrv_close()), apply the snapshot on the child node, and then
re-open the node (with .bdrv_open()).
In order for .bdrv_open() to attach the same child node that we had
before, we pass "file={child-node}" or "backing={child-node}" to it.
Therefore, when .bdrv_open() has returned success, we can assume that
bs->file or bs->backing (respectively) points to our original child
again. This is verified by an assertion.
All of this is not immediately clear from a quick glance at the code,
so add a comment to the assertion what it is for, and why it is valid.
It certainly confused Coverity.
Reported-by: Coverity (CID 1452774)
Signed-off-by: Max Reitz <mreitz@redhat.com>
Message-Id: <
20210503095418.31521-1-mreitz@redhat.com>
[mreitz: s/close/detach/]
Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com>
Thomas Huth [Tue, 15 Jun 2021 09:04:39 +0000 (11:04 +0200)]
ui: Make the DisplayType enum entries conditional
Libvirt's "domcapabilities" command has a way to state whether certain
graphic frontends are available in QEMU or not. Originally, libvirt
looked at the "--help" output of the QEMU binary to determine whether
SDL was available or not (by looking for the "-sdl" parameter in the
help text), but since libvirt stopped doing this analysis of the help
text, the detection of SDL is currently broken, see:
https://bugzilla.redhat.com/show_bug.cgi?id=
1790902
QEMU should provide a way via the QMP interface instead. A simple way,
without introducing additional commands, is to make the DisplayType
enum entries conditional, so that the enum only contains the entries if
the corresponding CONFIG_xxx switches have been set. This of course
only gives an indication which possibilities have been enabled during
compile-time of QEMU (and does not take into account whether modules
are later available or not for example - for this we'd need a separate
command), but anyway, this should already be good enough for the above
bug ticket, and it's a good idea anyway to make the QMP interface
conditional here, so let's simply do it.
Signed-off-by: Thomas Huth <thuth@redhat.com>
Message-Id: <
20210615090439.70926-1-thuth@redhat.com>
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Ahmed Abouzied [Tue, 1 Jun 2021 17:41:18 +0000 (19:41 +0200)]
Add display suboptions to man pages
Updates man pages with the suboptions for the `-display`.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/128
Buglink: https://bugs.launchpad.net/qemu/+bug/1620660
Signed-off-by: Ahmed Abouzied <email@aabouzied.com>
Message-Id: <
20210601174117.661-1-email@aabouzied.com>
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Akihiko Odaki [Thu, 17 Jun 2021 02:31:13 +0000 (11:31 +0900)]
input: Add lang1 and lang2 to QKeyCode
lang1 and lang2 represents the keys with the same names in the
keyboard/keypad usage page (0x07) included in the "HID Usage Tables for
Universal Serial Bus (USB)" version 1.22. Although the keys are
described as "Hangul/English toggle key" and "Hanja conversion key" in
the specification, the meaning depends on the variety of the keyboard,
and it will be used as the representations of Kana and Eisu keys on
Japanese Macs in qemu_input_map_osx_to_qcode, which is used by ui/gtk.
Signed-off-by: Akihiko Odaki <akihiko.odaki@gmail.com>
Message-Id: <
20210617023113.2441-2-akihiko.odaki@gmail.com>
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Akihiko Odaki [Wed, 16 Jun 2021 14:19:54 +0000 (23:19 +0900)]
ui/cocoa: Add clipboard support
Signed-off-by: Akihiko Odaki <akihiko.odaki@gmail.com>
Message-Id: <
20210616141954.54291-1-akihiko.odaki@gmail.com>
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Akihiko Odaki [Wed, 16 Jun 2021 14:19:10 +0000 (23:19 +0900)]
ui/cocoa: Set UI information
Signed-off-by: Akihiko Odaki <akihiko.odaki@gmail.com>
Message-Id: <
20210616141910.54188-1-akihiko.odaki@gmail.com>
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Akihiko Odaki [Tue, 22 Jun 2021 20:17:40 +0000 (05:17 +0900)]
coreaudio: Lock only the buffer
On macOS 11.3.1, Core Audio calls AudioDeviceIOProc after calling an
internal function named HALB_Mutex::Lock(), which locks a mutex in
HALB_IOThread::Entry(void*). HALB_Mutex::Lock() is also called in
AudioObjectGetPropertyData, which is called by coreaudio driver.
Therefore, a deadlock will occur if coreaudio driver calls
AudioObjectGetPropertyData while holding a lock for a mutex and tries
to lock the same mutex in AudioDeviceIOProc.
audioDeviceIOProc, which implements AudioDeviceIOProc in coreaudio
driver, requires an exclusive access for the device configuration and
the buffer. Fortunately, a mutex is necessary only for the buffer in
audioDeviceIOProc because a change for the device configuration occurs
only before setting up AudioDeviceIOProc or after stopping the playback
with AudioDeviceStop.
With this change, the mutex owned by the driver will only be used for
the buffer, and the device configuration change will be protected with
the implicit iothread mutex.
Signed-off-by: Akihiko Odaki <akihiko.odaki@gmail.com>
Message-id:
20210622201740.38005-1-akihiko.odaki@gmail.com
Message-Id: <
20210622201740.38005-1-akihiko.odaki@gmail.com>
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>