Stephen Boyd [Fri, 3 Apr 2020 22:09:55 +0000 (15:09 -0700)]
Merge branches 'clk-ti', 'clk-ingenic', 'clk-typo', 'clk-at91', 'clk-mmp2' and 'clk-arm-icst' into clk-next
- EHRPWM's TimeBase clock(TBCLK) for TI AM654 SoCs
- Support PMC clks on at91sam9n12, at91rm9200, sama5d3, and at91sam9g45 SoCs
- Fixes and improvements for the Marvell MMP2/MMP3 SoC clk drivers
* clk-ti:
clk: keystone: Add new driver to handle syscon based clocks
dt-bindings: clock: Add binding documentation for TI EHRPWM TBCLK
* clk-ingenic:
clk: ingenic/TCU: Fix round_rate returning error
clk: ingenic/jz4770: Exit with error if CGU init failed
clk: JZ4780: Add function for enable the second core.
clk: Ingenic: Add support for TCU of X1000.
* clk-typo:
clk: Fix trivia typo in comment exlusive => exclusive
* clk-at91:
clk: at91: add at91rm9200 pmc driver
clk: at91: add at91sam9n12 pmc driver
clk: at91: add sama5d3 pmc driver
clk: at91: add at91sam9g45 pmc driver
clk: at91: usb: introduce num_parents in driver's structure
clk: at91: usb: use proper usbs_mask
clk: at91: sam9x60: fix usb clock parents
clk: at91: usb: continue if clk_hw_round_rate() return zero
clk: at91: sam9x60: Don't use audio PLL
* clk-mmp2:
clk: mmp2: Fix bit masks for LCDC I/O and pixel clocks
clk: mmp2: Add clock for fifth SD HCI on MMP3
dt-bindings: marvell,mmp2: Add clock id for the fifth SD HCI on MMP3
clk: mmp2: Add clocks for the thermal sensors
dt-bindings: marvell,mmp2: Add clock ids for the thermal sensors
clk: mmp2: add the GPU clocks
dt-bindings: marvell,mmp2: Add clock ids for the GPU clocks
clk: mmp2: Add PLLs that are available on MMP3
dt-bindings: marvell,mmp2: Add clock ids for MMP3 PLLs
clk: mmp2: Check for MMP3
dt-bindings: clock: Add MMP3 compatible string
clk: mmp2: Stop pretending PLL outputs are constant
clk: mmp2: Add support for PLL clock sources
dt-bindings: clock: Convert marvell,mmp2-clock to json-schema
clk: mmp2: Constify some strings
clk: mmp2: Remove a unused prototype
* clk-arm-icst:
MAINTAINERS: dt: update reference for arm-integrator.txt
clk: versatile: Add device tree probing for IM-PD1 clocks
clk: versatile: Export icst_clk_setup()
dt-bindings: clock: Create YAML schema for ICST clocks
Stephen Boyd [Fri, 3 Apr 2020 22:09:32 +0000 (15:09 -0700)]
Merge branches 'clk-phase-errors', 'clk-amlogic', 'clk-renesas' and 'clk-allwinner' into clk-next
- Don't show clk phase when it is invalid
* clk-phase-errors:
clk: rockchip: fix mmc get phase
clk: Fix phase init check
clk: Bail out when calculating phase fails during clk registration
clk: Move rate and accuracy recalc to mostly consumer APIs
clk: Use 'parent' to shorten lines in __clk_core_init()
clk: Don't cache errors from clk_ops::get_phase()
* clk-amlogic:
clk: meson: meson8b: set audio output clock hierarchy
clk: meson: g12a: add support for the SPICC SCLK Source clocks
dt-bindings: clk: g12a-clkc: add SPICC SCLK Source clock IDs
clk: meson: gxbb: set audio output clock hierarchy
clk: meson: gxbb: add the gxl internal dac gate
dt-bindings: clk: meson: add the gxl internal dac gate
* clk-renesas:
dt-bindings: clock: renesas: cpg-mssr: Convert to json-schema
clk: renesas: rcar-usb2-clock-sel: Add reset_control
clk: renesas: rcar-usb2-clock-sel: Add multiple clocks management
dt-bindings: clock: renesas: rcar-usb2-clock-sel: Add power-domains and resets properties
dt-bindings: clock: renesas: rcar-usb2-clock-sel: Fix clock[-name]s properties
clk: renesas: Remove use of ARCH_R8A7795
clk: renesas: r8a77965: Add RPC clocks
clk: renesas: r8a7796: Add RPC clocks
clk: renesas: r8a7795: Add RPC clocks
clk: renesas: rcar-gen3: Add CCREE clocks
* clk-allwinner:
clk: sunxi-ng: sun8i-de2: Sort structures
clk: sunxi-ng: sun8i-de2: Add R40 specific quirks
clk: sunxi-ng: sun8i-de2: Add rotation core clocks and reset for A83T
clk: sunxi-ng: sun8i-de2: Don't reuse A83T resets
clk: sunxi-ng: sun8i-de2: H6 doesn't have rotate core
clk: sunxi-ng: sun8i-de2: Add rotation core clocks and reset for A64
clk: sunxi-ng: sun8i-de2: Split out H5 definitions
clk: sunxi-ng: a64: Export MBUS clock
Stephen Boyd [Fri, 3 Apr 2020 22:09:22 +0000 (15:09 -0700)]
Merge branches 'clk-samsung', 'clk-formatting', 'clk-si5341' and 'clk-socfpga' into clk-next
* clk-samsung:
clk: samsung: Remove redundant check in samsung_cmu_register_one
* clk-formatting:
clk: Fix continuation of of_clk_detect_critical()
* clk-si5341:
clk, clk-si5341: Support multiple input ports
* clk-socfpga:
clk: socfpga: stratix10: simplify parameter passing
clk: stratix10: use do_div() for 64-bit calculation
Mauro Carvalho Chehab [Mon, 23 Mar 2020 12:25:28 +0000 (13:25 +0100)]
MAINTAINERS: dt: update reference for arm-integrator.txt
This file was renamed. Update references accordingly.
Fixes: 78c7d8f96b6f ("dt-bindings: clock: Create YAML schema for ICST clocks")
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Link: https://lkml.kernel.org/r/491d2928a47f59da3636bc63103a5f63fec72b1a.1584966325.git.mchehab+huawei@kernel.org
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Lubomir Rintel [Mon, 9 Mar 2020 19:42:54 +0000 (20:42 +0100)]
clk: mmp2: Fix bit masks for LCDC I/O and pixel clocks
They were reversed because I read the datasheet upside down.
Actually there is no datasheet, but I ended up understanding the
comments in Open Firmware driver wrong.
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Link: https://lkml.kernel.org/r/20200309194254.29009-18-lkundrak@v3.sk
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Lubomir Rintel [Mon, 9 Mar 2020 19:42:53 +0000 (20:42 +0100)]
clk: mmp2: Add clock for fifth SD HCI on MMP3
There's one extra SDHCI on MMP3, used by the internal SD card on OLPC
XO-4. Add a clock for it.
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Link: https://lkml.kernel.org/r/20200309194254.29009-17-lkundrak@v3.sk
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Lubomir Rintel [Mon, 9 Mar 2020 19:42:52 +0000 (20:42 +0100)]
dt-bindings: marvell,mmp2: Add clock id for the fifth SD HCI on MMP3
There's one extra SDHCI on MMP3, used by the internal SD card on OLPC
XO-4. Add a clock for it.
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Link: https://lkml.kernel.org/r/20200309194254.29009-16-lkundrak@v3.sk
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Lubomir Rintel [Mon, 9 Mar 2020 19:42:51 +0000 (20:42 +0100)]
clk: mmp2: Add clocks for the thermal sensors
The register definitions gotten from OLPC Open Firmware.
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Link: https://lkml.kernel.org/r/20200309194254.29009-15-lkundrak@v3.sk
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Lubomir Rintel [Mon, 9 Mar 2020 19:42:50 +0000 (20:42 +0100)]
dt-bindings: marvell,mmp2: Add clock ids for the thermal sensors
There seems to be a single thermal sensor block on MMP2 and a couple
more on MMP3. Add definitions for their respective clocks.
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Link: https://lkml.kernel.org/r/20200309194254.29009-14-lkundrak@v3.sk
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Lubomir Rintel [Mon, 9 Mar 2020 19:42:49 +0000 (20:42 +0100)]
clk: mmp2: add the GPU clocks
MMP2 has a single GC860 core while MMP3 has a GC2000 and a GC300.
On both platforms there's an AXI bus interface clock that's common for
all GPUs and each GPU core has a separate clock.
Meaning of the relevant APMU_GPU bits were gotten from James Cameron's
message and [1], the OLPC OS kernel source [2] and Marvell's MMP3 tree.
[1] http://lists.laptop.org/pipermail/devel/2019-April/039053.html
[2] http://dev.laptop.org/git/olpc-kernel/commit/arch/arm/mach-mmp/mmp2.c?h=arm-3.0-wip&id=
8ce9f6122
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Link: https://lkml.kernel.org/r/20200309194254.29009-13-lkundrak@v3.sk
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Lubomir Rintel [Mon, 9 Mar 2020 19:42:48 +0000 (20:42 +0100)]
dt-bindings: marvell,mmp2: Add clock ids for the GPU clocks
MMP2 has a single GC860 core while MMP3 has a GC2000 and a GC300.
On both platforms there's an AXI bus interface clock that's common for
all GPUs and each GPU core has a separate clock.
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Link: https://lkml.kernel.org/r/20200309194254.29009-12-lkundrak@v3.sk
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Lubomir Rintel [Mon, 9 Mar 2020 19:42:46 +0000 (20:42 +0100)]
clk: mmp2: Add PLLs that are available on MMP3
There are more PLLs on MMP3 and are configured slightly differently.
Tested on a MMP3-based Dell Wyse 3020 machine.
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Link: https://lkml.kernel.org/r/20200309194254.29009-10-lkundrak@v3.sk
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Lubomir Rintel [Mon, 9 Mar 2020 19:42:45 +0000 (20:42 +0100)]
dt-bindings: marvell,mmp2: Add clock ids for MMP3 PLLs
MMP3 variant provides some more clocks. Add respective IDs.
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lkml.kernel.org/r/20200309194254.29009-9-lkundrak@v3.sk
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Lubomir Rintel [Mon, 9 Mar 2020 19:42:44 +0000 (20:42 +0100)]
clk: mmp2: Check for MMP3
The MMP3's are similar enough to MMP2, but there are differencies, such
are more clocks available on the newer model. We want to tell which
platform are we on.
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Link: https://lkml.kernel.org/r/20200309194254.29009-8-lkundrak@v3.sk
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Lubomir Rintel [Mon, 9 Mar 2020 19:42:43 +0000 (20:42 +0100)]
dt-bindings: clock: Add MMP3 compatible string
This binding describes the PMUs that are found on MMP3 as well. Add the
compatible strings and adjust the description.
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lkml.kernel.org/r/20200309194254.29009-7-lkundrak@v3.sk
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Lubomir Rintel [Mon, 9 Mar 2020 19:42:42 +0000 (20:42 +0100)]
clk: mmp2: Stop pretending PLL outputs are constant
The hardcoded values for PLL1 and PLL2 are wrong. PLL1 is slightly
off -- it defaults to 797.33 MHz, not 800 MHz. PLL2 is disabled by default,
but also configurable.
Tested on a MMP2-based OLPC XO-1.75 laptop, with PLL1=797.33 and various
values of PLL2 set via set-pll2-520mhz, set-pll2-910mhz and
set-pll2-988mhz Open Firmware words.
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Link: https://lkml.kernel.org/r/20200309194254.29009-6-lkundrak@v3.sk
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Lubomir Rintel [Mon, 9 Mar 2020 19:42:41 +0000 (20:42 +0100)]
clk: mmp2: Add support for PLL clock sources
The clk-of-mmp2 driver pretends that the clock outputs from the PLLs are
constant, but in fact they are configurable.
Add logic for obtaining the actual clock rates on MMP2 as well as MMP3.
There is no documentation for either SoC, but the "systemsetting" drivers
from Marvell GPL code dump provide some clue as far as MPMU registers on
MMP2 [1] and MMP3 [2] go.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/lkundrak/linux-mmp3-dell-ariel.git/tree/drivers/char/mmp2_systemsetting.c
[2] https://git.kernel.org/pub/scm/linux/kernel/git/lkundrak/linux-mmp3-dell-ariel.git/tree/drivers/char/mmp3_systemsetting.c
A separate commit will adjust the clk-of-mmp2 driver.
Tested on a MMP3-based Dell Wyse 3020 as well as MMP2-based OLPC
XO-1.75 laptop.
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Link: https://lkml.kernel.org/r/20200309194254.29009-5-lkundrak@v3.sk
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Lubomir Rintel [Mon, 9 Mar 2020 19:42:40 +0000 (20:42 +0100)]
dt-bindings: clock: Convert marvell,mmp2-clock to json-schema
Convert the fixed-factor-clock binding to DT schema format using
json-schema.
While at that, fix a couple of small errors: make the file base name
match the compatible string, add an example and document the reg-names
property.
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lkml.kernel.org/r/20200309194254.29009-4-lkundrak@v3.sk
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Lubomir Rintel [Mon, 9 Mar 2020 19:42:39 +0000 (20:42 +0100)]
clk: mmp2: Constify some strings
All the parent clock names for the muxes are constant. Add const.
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Link: https://lkml.kernel.org/r/20200309194254.29009-3-lkundrak@v3.sk
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Lubomir Rintel [Mon, 9 Mar 2020 19:42:38 +0000 (20:42 +0100)]
clk: mmp2: Remove a unused prototype
There is no mmp_clk_register_pll2() routine.
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Link: https://lkml.kernel.org/r/20200309194254.29009-2-lkundrak@v3.sk
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Alexandre Belloni [Fri, 14 Feb 2020 14:59:33 +0000 (15:59 +0100)]
clk: at91: add at91rm9200 pmc driver
Add a driver for the PMC clocks of the at91rm9200.
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Link: https://lkml.kernel.org/r/20200214145934.53648-1-alexandre.belloni@bootlin.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Linus Walleij [Wed, 19 Feb 2020 10:33:26 +0000 (11:33 +0100)]
clk: versatile: Add device tree probing for IM-PD1 clocks
As we want to move these clocks over to probe from the device
tree we add a device tree probing path.
The old platform data path will be deleted once we have the
device tree overall code in place.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lkml.kernel.org/r/20200219103326.81120-3-linus.walleij@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Linus Walleij [Wed, 19 Feb 2020 10:33:25 +0000 (11:33 +0100)]
clk: versatile: Export icst_clk_setup()
Export this clock setup method so we can register the
IM-PD1 clocks with common code in the next step.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lkml.kernel.org/r/20200219103326.81120-2-linus.walleij@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Linus Walleij [Wed, 19 Feb 2020 10:33:24 +0000 (11:33 +0100)]
dt-bindings: clock: Create YAML schema for ICST clocks
The ICST clocks used in the ARM Integrator, Versatile and
RealView platforms are updated to use YAML schema, and two
new ICST clocks used by the Integrator IM-PD1 logical module
are added in the process.
Cc: devicetree@vger.kernel.org
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lkml.kernel.org/r/20200219103326.81120-1-linus.walleij@linaro.org
[sboyd@kernel.org: Fix some typos]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Andy Shevchenko [Tue, 10 Mar 2020 13:55:07 +0000 (15:55 +0200)]
clk: Fix trivia typo in comment exlusive => exclusive
Fix trivia typo in comment exlusive => exclusive.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lkml.kernel.org/r/20200310135507.87959-1-andriy.shevchenko@linux.intel.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Paul Cercueil [Thu, 13 Feb 2020 16:19:52 +0000 (13:19 -0300)]
clk: ingenic/TCU: Fix round_rate returning error
When requesting a rate superior to the parent's rate, it would return
-EINVAL instead of simply returning the parent's rate like it should.
Fixes: 4f89e4b8f121 ("clk: ingenic: Add driver for the TCU clocks")
Cc: stable@vger.kernel.org
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Link: https://lkml.kernel.org/r/20200213161952.37460-2-paul@crapouillou.net
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Paul Cercueil [Thu, 13 Feb 2020 16:19:51 +0000 (13:19 -0300)]
clk: ingenic/jz4770: Exit with error if CGU init failed
Exit jz4770_cgu_init() if the 'cgu' pointer we get is NULL, since the
pointer is passed as argument to functions later on.
Fixes: 7a01c19007ad ("clk: Add Ingenic jz4770 CGU driver")
Cc: stable@vger.kernel.org
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Reported-by: kbuild test robot <lkp@intel.com>
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
Link: https://lkml.kernel.org/r/20200213161952.37460-1-paul@crapouillou.net
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Vignesh Raghavendra [Thu, 27 Feb 2020 05:35:29 +0000 (11:05 +0530)]
clk: keystone: Add new driver to handle syscon based clocks
On TI's AM654/J721e SoCs, certain clocks can be gated/ungated by setting
a single bit in SoC's System Control Module registers. Sometime more
than one clock control can be in the same register.
Add a driver to support such clocks using syscon framework. Driver
currently supports controlling EHRPWM's TimeBase clock(TBCLK) for AM654
SoC.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Link: https://lkml.kernel.org/r/20200227053529.16479-3-vigneshr@ti.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Vignesh Raghavendra [Thu, 27 Feb 2020 05:35:28 +0000 (11:05 +0530)]
dt-bindings: clock: Add binding documentation for TI EHRPWM TBCLK
Add DT bindings for TI EHRPWM's TimeBase clock (TBCLK) on TI's AM654 SoC.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Link: https://lkml.kernel.org/r/20200227053529.16479-2-vigneshr@ti.com
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
周琰杰 (Zhou Yanjie) [Thu, 20 Feb 2020 16:24:43 +0000 (00:24 +0800)]
clk: JZ4780: Add function for enable the second core.
Add "jz4780_core1_enable()" for enable the second core of JZ4780,
prepare for later commits.
Tested-by: H. Nikolaus Schaller <hns@goldelico.com>
Tested-by: Paul Boddie <paul@boddie.org.uk>
Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Link: https://lkml.kernel.org/r/1582215889-113034-3-git-send-email-zhouyanjie@wanyeetech.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
周琰杰 (Zhou Yanjie) [Tue, 17 Mar 2020 15:11:33 +0000 (23:11 +0800)]
clk: Ingenic: Add support for TCU of X1000.
X1000 has a different TCU, since X1000 OST has been independent of TCU.
This patch is add TCU support of X1000, and prepare for later OST driver.
Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
Link: https://lkml.kernel.org/r/1584457893-40418-3-git-send-email-zhouyanjie@wanyeetech.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Stephen Boyd [Mon, 16 Mar 2020 18:22:39 +0000 (11:22 -0700)]
Merge tag 'sunxi-clk-for-5.7' of https://git./linux/kernel/git/sunxi/linux into clk-allwinner
Pull Allwinner clk driver updates from Chen-Yu Tsai:
Changes consist mainly of cleanups for the display engine clock driver,
correcting clocks that don't exist. Also, the MBUS clock on the A64 is
exported for the device tree to consume.
* tag 'sunxi-clk-for-5.7' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
clk: sunxi-ng: sun8i-de2: Sort structures
clk: sunxi-ng: sun8i-de2: Add R40 specific quirks
clk: sunxi-ng: sun8i-de2: Add rotation core clocks and reset for A83T
clk: sunxi-ng: sun8i-de2: Don't reuse A83T resets
clk: sunxi-ng: sun8i-de2: H6 doesn't have rotate core
clk: sunxi-ng: sun8i-de2: Add rotation core clocks and reset for A64
clk: sunxi-ng: sun8i-de2: Split out H5 definitions
clk: sunxi-ng: a64: Export MBUS clock
Stephen Boyd [Mon, 16 Mar 2020 18:15:10 +0000 (11:15 -0700)]
Merge tag 'clk-renesas-for-v5.7-tag2' of git://git./linux/kernel/git/geert/renesas-drivers into clk-renesas
Pull more Renesas clk driver updates from Geert Uytterhoeven:
- Improved clock/reset handling for the R-Car USB2 Clock Selector
- Conversion to json-schema of the Renesas CPG/MSSR DT bindings
* tag 'clk-renesas-for-v5.7-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
dt-bindings: clock: renesas: cpg-mssr: Convert to json-schema
clk: renesas: rcar-usb2-clock-sel: Add reset_control
clk: renesas: rcar-usb2-clock-sel: Add multiple clocks management
dt-bindings: clock: renesas: rcar-usb2-clock-sel: Add power-domains and resets properties
dt-bindings: clock: renesas: rcar-usb2-clock-sel: Fix clock[-name]s properties
Geert Uytterhoeven [Tue, 3 Mar 2020 09:48:48 +0000 (10:48 +0100)]
dt-bindings: clock: renesas: cpg-mssr: Convert to json-schema
Convert the Renesas Clock Pulse Generator / Module Standby and Software
Reset Device Tree binding documentation to json-schema.
Note that #reset-cells was incorrecty marked a required property for
RZ/A2 before.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20200303094848.23670-1-geert+renesas@glider.be
Yoshihiro Shimoda [Wed, 4 Mar 2020 06:42:17 +0000 (15:42 +0900)]
clk: renesas: rcar-usb2-clock-sel: Add reset_control
This hardware needs to deassert resets of both host and peripheral.
So, this patch adds reset control.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/1583304137-28482-5-git-send-email-yoshihiro.shimoda.uh@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Yoshihiro Shimoda [Wed, 4 Mar 2020 06:42:16 +0000 (15:42 +0900)]
clk: renesas: rcar-usb2-clock-sel: Add multiple clocks management
This hardware needs to enable clocks of both host and peripheral.
So, this patch adds multiple clocks management.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/1583304137-28482-4-git-send-email-yoshihiro.shimoda.uh@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Yoshihiro Shimoda [Wed, 4 Mar 2020 06:42:15 +0000 (15:42 +0900)]
dt-bindings: clock: renesas: rcar-usb2-clock-sel: Add power-domains and resets properties
This patch adds missing required properties of power-domains and resets.
Fortunately, no one has this device node for now, so that we don't
need to think of backward compatibility.
Fixes: 311accb64570 ("clk: renesas: rcar-usb2-clock-sel: Add R-Car USB 2.0 clock selector PHY")
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/1583304137-28482-3-git-send-email-yoshihiro.shimoda.uh@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Yoshihiro Shimoda [Wed, 4 Mar 2020 06:42:14 +0000 (15:42 +0900)]
dt-bindings: clock: renesas: rcar-usb2-clock-sel: Fix clock[-name]s properties
Since the hardware requires to enable both USB 2.0 host and peripheral
functional clock, this patch fixes the documentation.
Fortunately, no one has this device node for now, so that we don't
need to think of backward compatibility.
Fixes: 311accb64570 ("clk: renesas: rcar-usb2-clock-sel: Add R-Car USB 2.0 clock selector PHY")
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/1583304137-28482-2-git-send-email-yoshihiro.shimoda.uh@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Stephen Boyd [Fri, 6 Mar 2020 21:11:42 +0000 (13:11 -0800)]
Merge tag 'clk-meson-v5.7-1' of https://github.com/BayLibre/clk-meson into clk-amlogic
Pull Amlogic clk driver updates from Jerome Brunet:
- Update audio clock gate hierarchy for meson8 and gxbb
- Update g12a spicc clock sources
* tag 'clk-meson-v5.7-1' of https://github.com/BayLibre/clk-meson:
clk: meson: meson8b: set audio output clock hierarchy
clk: meson: g12a: add support for the SPICC SCLK Source clocks
dt-bindings: clk: g12a-clkc: add SPICC SCLK Source clock IDs
clk: meson: gxbb: set audio output clock hierarchy
clk: meson: gxbb: add the gxl internal dac gate
dt-bindings: clk: meson: add the gxl internal dac gate
Stephen Boyd [Fri, 6 Mar 2020 20:07:19 +0000 (12:07 -0800)]
Merge tag 'clk-renesas-for-v5.7-tag1' of git://git./linux/kernel/git/geert/renesas-drivers into clk-renesas
Pull Renesas clk driver updates from Geert Uytterhoeven:
- Add Crypto clocks on R-Car M3-W/W+, M3-N, E3, and D3
- Add RPC (QSPI/HyperFLASH) clocks on R-Car H3, M3-W/W+, and M3-N
* tag 'clk-renesas-for-v5.7-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
clk: renesas: Remove use of ARCH_R8A7795
clk: renesas: r8a77965: Add RPC clocks
clk: renesas: r8a7796: Add RPC clocks
clk: renesas: r8a7795: Add RPC clocks
clk: renesas: rcar-gen3: Add CCREE clocks
Jerome Brunet [Tue, 3 Mar 2020 19:29:56 +0000 (20:29 +0100)]
clk: rockchip: fix mmc get phase
If the mmc clock has no rate, it can be assumed to be constant.
In such case, there is no measurable phase shift. Just return 0
in this case instead of returning an error.
Fixes: 2760878662a2 ("clk: Bail out when calculating phase fails during clk registration")
Tested-by: Markus Reichl <m.reichl@fivetechno.de>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://lkml.kernel.org/r/20200303192956.64410-1-jbrunet@baylibre.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Maxime Ripard [Tue, 25 Feb 2020 13:42:48 +0000 (14:42 +0100)]
clk: Fix phase init check
Commit
2760878662a2 ("clk: Bail out when calculating phase fails during
clk registration") introduced a check on error values at the time the
clock is registered to bail out when such an error occurs. However, it
doesn't check whether the returned value is positive which will happen
if the driver returns a non-zero phase. Since a phase is usually a
non-zero positive number this ends up returning something that isn't 0
to the caller of __clk_core_init(), making most clks fail to register
if they implement a phase clk op and return anything besides 0 for the
phase.
Fix this by returning the error if phase is less than zero or just
return zero if the phase is a positive number.
Fixes: 2760878662a2 ("clk: Bail out when calculating phase fails during clk registration")
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lkml.kernel.org/r/20200225134248.919889-1-maxime@cerno.tech
Reported-by: "kernelci.org bot" <bot@kernelci.org>
[sboyd@kernel.org: Reword commit text to provide clarity]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Geert Uytterhoeven [Tue, 18 Feb 2020 11:25:25 +0000 (12:25 +0100)]
clk: renesas: Remove use of ARCH_R8A7795
CONFIG_ARCH_R8A7795 was split in CONFIG_ARCH_R8A77950 and
CONFIG_ARCH_R8A77951 in commit
b925adfceb529389 ("soc: renesas: Add
ARCH_R8A7795[01] for existing R-Car H3"), so its users can be removed.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20200218112525.5834-1-geert+renesas@glider.be
Martin Blumenstingl [Thu, 20 Feb 2020 20:44:33 +0000 (21:44 +0100)]
clk: meson: meson8b: set audio output clock hierarchy
The aiu devices peripheral clocks needs the aiu and aiu_glue clocks to
operate. Reflect this hierarchy in the clock tree.
Fixes: e31a1900c1ff73 ("meson: clk: Add support for clock gates")
Suggested-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Neil Armstrong [Wed, 19 Feb 2020 08:49:28 +0000 (09:49 +0100)]
clk: meson: g12a: add support for the SPICC SCLK Source clocks
This adds the clocks used for the Amlogic G12A and compatible SoCs SPICC
controller to provide a more complete range of frequencies instead of the
SPICC internal divider over Xtal.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Jerome Brunet [Wed, 19 Feb 2020 17:40:45 +0000 (18:40 +0100)]
Merge branch 'v5.7/dt' into v5.7/drivers
Neil Armstrong [Wed, 19 Feb 2020 08:49:27 +0000 (09:49 +0100)]
dt-bindings: clk: g12a-clkc: add SPICC SCLK Source clock IDs
Add clock ids used by the SPICC Controllers of the G12A and compatible SoCs
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Jerome Brunet [Wed, 22 Jan 2020 10:04:51 +0000 (11:04 +0100)]
clk: meson: gxbb: set audio output clock hierarchy
The aiu devices peripheral clocks needs the aiu and aiu_glue clocks to
operate. Reflect this hierarchy in the gxbb clock tree.
Fixes: 738f66d3211d ("clk: gxbb: add AmLogic GXBB clk controller driver")
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Jerome Brunet [Wed, 22 Jan 2020 10:04:50 +0000 (11:04 +0100)]
clk: meson: gxbb: add the gxl internal dac gate
Add the ACODEC clock gate to the gxl clk controller driver
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Jerome Brunet [Wed, 22 Jan 2020 10:04:49 +0000 (11:04 +0100)]
dt-bindings: clk: meson: add the gxl internal dac gate
Add the gxl ACODEC clock id to the gxbb clock controller bindings
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Dinh Nguyen [Tue, 14 Jan 2020 16:07:26 +0000 (10:07 -0600)]
clk: socfpga: stratix10: simplify parameter passing
Just pass the clock pointer structure to the various register functions.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Link: https://lkml.kernel.org/r/20200114160726.19771-2-dinguyen@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Dinh Nguyen [Tue, 14 Jan 2020 16:07:25 +0000 (10:07 -0600)]
clk: stratix10: use do_div() for 64-bit calculation
do_div() macro to perform u64 division and guards against overflow if
the result is too large for the unsigned long return type.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Link: https://lkml.kernel.org/r/20200114160726.19771-1-dinguyen@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Geert Uytterhoeven [Fri, 6 Dec 2019 13:34:14 +0000 (14:34 +0100)]
clk: Fix continuation of of_clk_detect_critical()
The second line of the of_clk_detect_critical() function signature is
not indented according to coding style.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lkml.kernel.org/r/20191206133414.23925-1-geert+renesas@glider.be
Acked-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Aditya Pakki [Tue, 21 Jan 2020 23:33:49 +0000 (17:33 -0600)]
clk: samsung: Remove redundant check in samsung_cmu_register_one
Consistent with other instances of samsung_clk_init, the check
if ctx is NULL is redundant. The function currently does not
return NULL.
Signed-off-by: Aditya Pakki <pakki001@umn.edu>
Link: https://lkml.kernel.org/r/20200121233349.28627-1-pakki001@umn.edu
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Alexandre Belloni [Thu, 16 Jan 2020 17:23:16 +0000 (18:23 +0100)]
clk: at91: add at91sam9n12 pmc driver
Add a driver for the PMC clocks of the at91sam9n12 family.
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Link: https://lkml.kernel.org/r/20200116172316.426703-1-alexandre.belloni@bootlin.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Alexandre Belloni [Fri, 10 Jan 2020 22:30:33 +0000 (23:30 +0100)]
clk: at91: add sama5d3 pmc driver
Add a driver for the PMC clocks of the sama5d3.
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Link: https://lkml.kernel.org/r/20200110223033.1261791-1-alexandre.belloni@bootlin.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Alexandre Belloni [Fri, 17 Jan 2020 21:05:29 +0000 (22:05 +0100)]
clk: at91: add at91sam9g45 pmc driver
Add a driver for the PMC clocks of the at91sam9g45 family.
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Link: https://lkml.kernel.org/r/20200117210529.17490-1-alexandre.belloni@bootlin.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Claudiu Beznea [Fri, 17 Jan 2020 11:36:49 +0000 (13:36 +0200)]
clk: at91: usb: introduce num_parents in driver's structure
SAM9X60 USB clock may have up to 3 parents. Save the number of parents in
driver's data structure and validate against it when setting parent.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lkml.kernel.org/r/1579261009-4573-5-git-send-email-claudiu.beznea@microchip.com
Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Claudiu Beznea [Fri, 17 Jan 2020 11:36:48 +0000 (13:36 +0200)]
clk: at91: usb: use proper usbs_mask
Use usbs_mask passed as argument. The usbs_mask is different for
SAM9X60.
Fixes: 2423eeaead6f8 ("clk: at91: usb: Add sam9x60 support")
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lkml.kernel.org/r/1579261009-4573-4-git-send-email-claudiu.beznea@microchip.com
Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Claudiu Beznea [Fri, 17 Jan 2020 11:36:47 +0000 (13:36 +0200)]
clk: at91: sam9x60: fix usb clock parents
SAM9X60's USB clock has 3 parents: plla, upll and main_osc.
Fixes: 01e2113de9a5 ("clk: at91: add sam9x60 pmc driver")
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lkml.kernel.org/r/1579261009-4573-3-git-send-email-claudiu.beznea@microchip.com
Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Claudiu Beznea [Fri, 17 Jan 2020 11:36:46 +0000 (13:36 +0200)]
clk: at91: usb: continue if clk_hw_round_rate() return zero
clk_hw_round_rate() may call round rate function of its parents. In case
of SAM9X60 two of USB parrents are PLLA and UPLL. These clocks are
controlled by clk-sam9x60-pll.c driver. The round rate function for this
driver is sam9x60_pll_round_rate() which call in turn
sam9x60_pll_get_best_div_mul(). In case the requested rate is not in the
proper range (rate < characteristics->output[0].min &&
rate > characteristics->output[0].max) the sam9x60_pll_round_rate() will
return a negative number to its caller (called by
clk_core_round_rate_nolock()). clk_hw_round_rate() will return zero in
case a negative number is returned by clk_core_round_rate_nolock(). With
this, the USB clock will continue its rate computation even caller of
clk_hw_round_rate() returned an error. With this, the USB clock on SAM9X60
may not chose the best parent. I detected this after a suspend/resume
cycle on SAM9X60.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lkml.kernel.org/r/1579261009-4573-2-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Codrin Ciubotariu [Fri, 31 Jan 2020 11:58:16 +0000 (13:58 +0200)]
clk: at91: sam9x60: Don't use audio PLL
On sam9x60, there is not audio PLL and so I2S and classD have to use one
of the best matching parents for their generated clock.
Fixes: 01e2113de9a5 ("clk: at91: add sam9x60 pmc driver")
Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com>
Link: https://lkml.kernel.org/r/20200131115816.12483-1-codrin.ciubotariu@microchip.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Stephen Boyd [Wed, 5 Feb 2020 23:28:02 +0000 (15:28 -0800)]
clk: Bail out when calculating phase fails during clk registration
Bail out of clk registration if we fail to get the phase for a clk that
has a clk_ops::get_phase() callback. Print a warning too so that driver
authors can easily figure out that some clk is unable to read back phase
information at boot.
Cc: Douglas Anderson <dianders@chromium.org>
Cc: Heiko Stuebner <heiko@sntech.de>
Suggested-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lkml.kernel.org/r/20200205232802.29184-5-sboyd@kernel.org
Acked-by: Jerome Brunet <jbrunet@baylibre.com>
Stephen Boyd [Wed, 5 Feb 2020 23:28:01 +0000 (15:28 -0800)]
clk: Move rate and accuracy recalc to mostly consumer APIs
There's some confusion about when recalc is done for the rate and
accuracy clk consumer APIs in relation to the prepare lock being taken.
Oddly enough, we take the lock again in debugfs APIs so that we can call
the internal "clk_core" APIs to get these fields with any necessary
recalculations. Instead of having this confusion, let's introduce a
recalc variant of these two consumer APIs as internal helpers and call
them from the consumer APIs and the debugfs code so that we don't take
the lock more than once.
Cc: Douglas Anderson <dianders@chromium.org>
Cc: Heiko Stuebner <heiko@sntech.de>
Cc: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lkml.kernel.org/r/20200205232802.29184-4-sboyd@kernel.org
Acked-by: Jerome Brunet <jbrunet@baylibre.com>
Stephen Boyd [Wed, 5 Feb 2020 23:28:00 +0000 (15:28 -0800)]
clk: Use 'parent' to shorten lines in __clk_core_init()
Some lines are getting long in this function. Let's move 'parent' up to
the top of the function and use it in many places whenever there is a
parent for a clk. This shortens some lines by avoiding core->parent->
indirections.
Cc: Douglas Anderson <dianders@chromium.org>
Cc: Heiko Stuebner <heiko@sntech.de>
Cc: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lkml.kernel.org/r/20200205232802.29184-3-sboyd@kernel.org
Acked-by: Jerome Brunet <jbrunet@baylibre.com>
Stephen Boyd [Wed, 5 Feb 2020 23:27:59 +0000 (15:27 -0800)]
clk: Don't cache errors from clk_ops::get_phase()
We don't check for errors from clk_ops::get_phase() before storing away
the result into the clk_core::phase member. This can lead to some fairly
confusing debugfs information if these ops do return an error. Let's
skip the store when this op fails to fix this. While we're here, move
the locking outside of clk_core_get_phase() to simplify callers from
the debugfs side.
Cc: Douglas Anderson <dianders@chromium.org>
Cc: Heiko Stuebner <heiko@sntech.de>
Cc: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lkml.kernel.org/r/20200205232802.29184-2-sboyd@kernel.org
Acked-by: Jerome Brunet <jbrunet@baylibre.com>
Jernej Skrabec [Tue, 11 Feb 2020 18:59:36 +0000 (19:59 +0100)]
clk: sunxi-ng: sun8i-de2: Sort structures
V3s quirks are not in right place. Move it.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Jernej Skrabec [Tue, 11 Feb 2020 18:59:35 +0000 (19:59 +0100)]
clk: sunxi-ng: sun8i-de2: Add R40 specific quirks
R40 is actually very similar to A64, but it doesn't have mixer1 reset.
This means it's clocks and resets combination is unique and R40 specific
quirks are needed.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Jernej Skrabec [Tue, 11 Feb 2020 18:59:34 +0000 (19:59 +0100)]
clk: sunxi-ng: sun8i-de2: Add rotation core clocks and reset for A83T
A83T structures don't have clocks and reset for rotation core. Add them.
Fixes: 763c5bd045b1 ("clk: sunxi-ng: add support for DE2 CCU")
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Jernej Skrabec [Tue, 11 Feb 2020 18:59:33 +0000 (19:59 +0100)]
clk: sunxi-ng: sun8i-de2: Don't reuse A83T resets
Currently, V3s and H3 reuse A83T reset structure. However, A83T contains
additional core for rotation, which is not present in V3s and H3.
Make new reset structure for H3 and let V3s reuse it. A83T reset
structure will be amended in subsequent commit.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Jernej Skrabec [Tue, 11 Feb 2020 18:59:32 +0000 (19:59 +0100)]
clk: sunxi-ng: sun8i-de2: H6 doesn't have rotate core
DE3 documentation regarding presence of rotate core in H6 is a bit
confusing. Register descriptions mention bits for enabling rotate core
clocks and reset, but general overview doesn't list it as feature of H6
display engine, BSP kernel doesn't support it and there is no interrupt
listed for it. Manual poking registers also didn't reveal presence of
rotate core.
Let's assume there isn't any rotate core on H6 present and remove
related clocks. With that done, structures are same as those for H5, so
just reuse H5 structure.
Fixes: 56808da9f97f ("clk: sunxi-ng: Add support for H6 DE3 clocks")
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Jernej Skrabec [Tue, 11 Feb 2020 18:59:31 +0000 (19:59 +0100)]
clk: sunxi-ng: sun8i-de2: Add rotation core clocks and reset for A64
A64 has rotation core which needs clocks and reset. Because there is no
appropriate structures available, make a separate, A64 specific
structures.
Fixes: cf4881c12935 ("clk: sunxi-ng: fix the A64/H5 clock description of DE2 CCU")
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Jernej Skrabec [Tue, 11 Feb 2020 18:59:30 +0000 (19:59 +0100)]
clk: sunxi-ng: sun8i-de2: Split out H5 definitions
H5 has less clocks and resets than A64. Currently that's not obvious
because A64 is missing rotation core related clocks and reset.
Split out H5 definition. A64 structures will be fixed in subsequent
commit.
Note that this patch depends on commit
19368d99746e ("clk: sunxi-ng:
add support for Allwinner H3 DE2 CCU") for the H3 clock list.
Fixes: 763c5bd045b1 ("clk: sunxi-ng: add support for DE2 CCU")
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Jernej Skrabec [Mon, 10 Feb 2020 17:06:53 +0000 (18:06 +0100)]
clk: sunxi-ng: a64: Export MBUS clock
MBUS clock will be referenced in MBUS controller node.
Export it.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Dirk Behme [Mon, 3 Feb 2020 07:29:01 +0000 (08:29 +0100)]
clk: renesas: r8a77965: Add RPC clocks
Describe the RPCSRC internal clock and the RPC[D2] clocks derived from
it, as well as the RPC-IF module clock, in the R-Car M3-N (R8A77965)
CPG/MSSR driver.
Inspired by commit
94e3935b5756 ("clk: renesas: r8a77980: Add RPC clocks").
Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com>
Link: https://lore.kernel.org/r/20200203072901.31548-3-dirk.behme@de.bosch.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Dirk Behme [Mon, 3 Feb 2020 07:29:00 +0000 (08:29 +0100)]
clk: renesas: r8a7796: Add RPC clocks
Describe the RPCSRC internal clock and the RPC[D2] clocks derived from
it, as well as the RPC-IF module clock, in the R-Car M3-W/M3-W+
(R8A7796) CPG/MSSR driver.
Inspired by commit
94e3935b5756 ("clk: renesas: r8a77980: Add RPC clocks").
Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com>
Link: https://lore.kernel.org/r/20200203072901.31548-2-dirk.behme@de.bosch.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Dirk Behme [Mon, 3 Feb 2020 07:28:59 +0000 (08:28 +0100)]
clk: renesas: r8a7795: Add RPC clocks
Describe the RPCSRC internal clock and the RPC[D2] clocks derived from
it, as well as the RPC-IF module clock, in the R-Car H3 (R8A7795)
CPG/MSSR driver.
Inspired by commit
94e3935b5756 ("clk: renesas: r8a77980: Add RPC clocks").
Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com>
Link: https://lore.kernel.org/r/20200203072901.31548-1-dirk.behme@de.bosch.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Geert Uytterhoeven [Fri, 24 Jan 2020 13:31:37 +0000 (14:31 +0100)]
clk: renesas: rcar-gen3: Add CCREE clocks
Add the CryptoCell module clocks and their parents for the CryptoCell
instances in the various Renesas R-Car Gen3 SoCs that do not have
support for them yet in their clock drivers (M3-W/W+, M3-N, E3, D3).
The R-Car H3 clock driver already supports these clocks.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20200124133137.15921-1-geert+renesas@glider.be
Linus Torvalds [Mon, 10 Feb 2020 00:08:48 +0000 (16:08 -0800)]
Linux 5.6-rc1
Linus Torvalds [Mon, 10 Feb 2020 00:05:50 +0000 (16:05 -0800)]
Merge tag 'kbuild-v5.6-2' of git://git./linux/kernel/git/masahiroy/linux-kbuild
Pull more Kbuild updates from Masahiro Yamada:
- fix randconfig to generate a sane .config
- rename hostprogs-y / always to hostprogs / always-y, which are more
natual syntax.
- optimize scripts/kallsyms
- fix yes2modconfig and mod2yesconfig
- make multiple directory targets ('make foo/ bar/') work
* tag 'kbuild-v5.6-2' of git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-kbuild:
kbuild: make multiple directory targets work
kconfig: Invalidate all symbols after changing to y or m.
kallsyms: fix type of kallsyms_token_table[]
scripts/kallsyms: change table to store (strcut sym_entry *)
scripts/kallsyms: rename local variables in read_symbol()
kbuild: rename hostprogs-y/always to hostprogs/always-y
kbuild: fix the document to use extra-y for vmlinux.lds
kconfig: fix broken dependency in randconfig-generated .config
Linus Torvalds [Sun, 9 Feb 2020 23:51:46 +0000 (15:51 -0800)]
Merge tag 'zonefs-5.6-rc1' of git://git./linux/kernel/git/dlemoal/zonefs
Pull new zonefs file system from Damien Le Moal:
"Zonefs is a very simple file system exposing each zone of a zoned
block device as a file.
Unlike a regular file system with native zoned block device support
(e.g. f2fs or the on-going btrfs effort), zonefs does not hide the
sequential write constraint of zoned block devices to the user. As a
result, zonefs is not a POSIX compliant file system. Its goal is to
simplify the implementation of zoned block devices support in
applications by replacing raw block device file accesses with a richer
file based API, avoiding relying on direct block device file ioctls
which may be more obscure to developers.
One example of this approach is the implementation of LSM
(log-structured merge) tree structures (such as used in RocksDB and
LevelDB) on zoned block devices by allowing SSTables to be stored in a
zone file similarly to a regular file system rather than as a range of
sectors of a zoned device. The introduction of the higher level
construct "one file is one zone" can help reducing the amount of
changes needed in the application while at the same time allowing the
use of zoned block devices with various programming languages other
than C.
Zonefs IO management implementation uses the new iomap generic code.
Zonefs has been successfully tested using a functional test suite
(available with zonefs userland format tool on github) and a prototype
implementation of LevelDB on top of zonefs"
* tag 'zonefs-5.6-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/dlemoal/zonefs:
zonefs: Add documentation
fs: New zonefs file system
Marc Zyngier [Sun, 9 Feb 2020 22:48:50 +0000 (22:48 +0000)]
irqchip/gic-v4.1: Avoid 64bit division for the sake of 32bit ARM
In order to allow the GICv4 code to link properly on 32bit ARM,
make sure we don't use 64bit divisions when it isn't strictly
necessary.
Fixes: 4e6437f12d6e ("irqchip/gic-v4.1: Ensure L2 vPE table is allocated at RD level")
Reported-by: Stephen Rothwell <sfr@canb.auug.org.au>
Cc: Zenghui Yu <yuzenghui@huawei.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Linus Torvalds [Sun, 9 Feb 2020 21:27:17 +0000 (13:27 -0800)]
Merge tag '5.6-rc-smb3-plugfest-patches' of git://git.samba.org/sfrench/cifs-2.6
Pull cifs fixes from Steve French:
"13 cifs/smb3 patches, most from testing at the SMB3 plugfest this week:
- Important fix for multichannel and for modefromsid mounts.
- Two reconnect fixes
- Addition of SMB3 change notify support
- Backup tools fix
- A few additional minor debug improvements (tracepoints and
additional logging found useful during testing this week)"
* tag '5.6-rc-smb3-plugfest-patches' of git://git.samba.org/sfrench/cifs-2.6:
smb3: Add defines for new information level, FileIdInformation
smb3: print warning once if posix context returned on open
smb3: add one more dynamic tracepoint missing from strict fsync path
cifs: fix mode bits from dir listing when mounted with modefromsid
cifs: fix channel signing
cifs: add SMB3 change notification support
cifs: make multichannel warning more visible
cifs: fix soft mounts hanging in the reconnect code
cifs: Add tracepoints for errors on flush or fsync
cifs: log warning message (once) if out of disk space
cifs: fail i/o on soft mounts if sessionsetup errors out
smb3: fix problem with null cifs super block with previous patch
SMB3: Backup intent flag missing from some more ops
Linus Torvalds [Sun, 9 Feb 2020 20:41:00 +0000 (12:41 -0800)]
Merge branch 'work.vboxsf' of git://git./linux/kernel/git/viro/vfs
Pull vboxfs from Al Viro:
"This is the VirtualBox guest shared folder support by Hans de Goede,
with fixups for fs_parse folded in to avoid bisection hazards from
those API changes..."
* 'work.vboxsf' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs:
fs: Add VirtualBox guest shared folder (vboxsf) support
Linus Torvalds [Sun, 9 Feb 2020 20:11:12 +0000 (12:11 -0800)]
Merge tag 'x86-urgent-2020-02-09' of git://git./linux/kernel/git/tip/tip
Pull x86 fixes from Thomas Gleixner:
"A set of fixes for X86:
- Ensure that the PIT is set up when the local APIC is disable or
configured in legacy mode. This is caused by an ordering issue
introduced in the recent changes which skip PIT initialization when
the TSC and APIC frequencies are already known.
- Handle malformed SRAT tables during early ACPI parsing which caused
an infinite loop anda boot hang.
- Fix a long standing race in the affinity setting code which affects
PCI devices with non-maskable MSI interrupts. The problem is caused
by the non-atomic writes of the MSI address (destination APIC id)
and data (vector) fields which the device uses to construct the MSI
message. The non-atomic writes are mandated by PCI.
If both fields change and the device raises an interrupt after
writing address and before writing data, then the MSI block
constructs a inconsistent message which causes interrupts to be
lost and subsequent malfunction of the device.
The fix is to redirect the interrupt to the new vector on the
current CPU first and then switch it over to the new target CPU.
This allows to observe an eventually raised interrupt in the
transitional stage (old CPU, new vector) to be observed in the APIC
IRR and retriggered on the new target CPU and the new vector.
The potential spurious interrupts caused by this are harmless and
can in the worst case expose a buggy driver (all handlers have to
be able to deal with spurious interrupts as they can and do happen
for various reasons).
- Add the missing suspend/resume mechanism for the HYPERV hypercall
page which prevents resume hibernation on HYPERV guests. This
change got lost before the merge window.
- Mask the IOAPIC before disabling the local APIC to prevent
potentially stale IOAPIC remote IRR bits which cause stale
interrupt lines after resume"
* tag 'x86-urgent-2020-02-09' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
x86/apic: Mask IOAPIC entries when disabling the local APIC
x86/hyperv: Suspend/resume the hypercall page for hibernation
x86/apic/msi: Plug non-maskable MSI affinity race
x86/boot: Handle malformed SRAT tables during early ACPI parsing
x86/timer: Don't skip PIT setup when APIC is disabled or in legacy mode
Linus Torvalds [Sun, 9 Feb 2020 20:09:43 +0000 (12:09 -0800)]
Merge tag 'smp-urgent-2020-02-09' of git://git./linux/kernel/git/tip/tip
Pull SMP fixes from Thomas Gleixner:
"Two fixes for the SMP related functionality:
- Make the UP version of smp_call_function_single() match SMP
semantics when called for a not available CPU. Instead of emitting
a warning and assuming that the function call target is CPU0,
return a proper error code like the SMP version does.
- Remove a superfluous check in smp_call_function_many_cond()"
* tag 'smp-urgent-2020-02-09' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
smp/up: Make smp_call_function_single() match SMP semantics
smp: Remove superfluous cond_func check in smp_call_function_many_cond()
Linus Torvalds [Sun, 9 Feb 2020 20:04:09 +0000 (12:04 -0800)]
Merge tag 'perf-urgent-2020-02-09' of git://git./linux/kernel/git/tip/tip
Pull perf fixes from Thomas Gleixner:
"A set of fixes and improvements for the perf subsystem:
Kernel fixes:
- Install cgroup events to the correct CPU context to prevent a
potential list double add
- Prevent an integer underflow in the perf mlock accounting
- Add a missing prototype for arch_perf_update_userpage()
Tooling:
- Add a missing unlock in the error path of maps__insert() in perf
maps.
- Fix the build with the latest libbfd
- Fix the perf parser so it does not delete parse event terms, which
caused a regression for using perf with the ARM CoreSight as the
sink configuration was missing due to the deletion.
- Fix the double free in the perf CPU map merging test case
- Add the missing ustring support for the perf probe command"
* tag 'perf-urgent-2020-02-09' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
perf maps: Add missing unlock to maps__insert() error case
perf probe: Add ustring support for perf probe command
perf: Make perf able to build with latest libbfd
perf test: Fix test case Merge cpu map
perf parse: Copy string to perf_evsel_config_term
perf parse: Refactor 'struct perf_evsel_config_term'
kernel/events: Add a missing prototype for arch_perf_update_userpage()
perf/cgroups: Install cgroup events to correct cpuctx
perf/core: Fix mlock accounting in perf_mmap()
Linus Torvalds [Sun, 9 Feb 2020 20:00:12 +0000 (12:00 -0800)]
Merge tag 'timers-urgent-2020-02-09' of git://git./linux/kernel/git/tip/tip
Pull timer fixes from Thomas Gleixner:
"Two small fixes for the time(r) subsystem:
- Handle a subtle race between the clocksource watchdog and a
concurrent clocksource watchdog stop/start sequence correctly to
prevent a timer double add bug.
- Fix the file path for the core time namespace file"
* tag 'timers-urgent-2020-02-09' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
clocksource: Prevent double add_timer_on() for watchdog_timer
MAINTAINERS: Correct path to time namespace source file
Linus Torvalds [Sun, 9 Feb 2020 19:56:41 +0000 (11:56 -0800)]
Merge tag 'irq-urgent-2020-02-09' of git://git./linux/kernel/git/tip/tip
Pull interrupt fixes from Thomas Gleixner:
"A set of fixes for the interrupt subsystem:
- Provision only ACPI enabled redistributors on GICv3
- Use the proper command colums when building the INVALL command for
the GICv3-ITS
- Ensure the allocation of the L2 vPE table for GICv4.1
- Correct the GICv4.1 VPROBASER programming so it uses the proper
size
- A set of small GICv4.1 tidy up patches
- Configuration cleanup for C-SKY interrupt chip
- Clarify the function documentation for irq_set_wake() to document
that the wakeup functionality is orthogonal to the irq
disable/enable mechanism"
* tag 'irq-urgent-2020-02-09' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
irqchip/gic-v3-its: Rename VPENDBASER/VPROPBASER accessors
irqchip/gic-v3-its: Remove superfluous WARN_ON
irqchip/gic-v4.1: Drop 'tmp' in inherit_vpe_l1_table_from_rd()
irqchip/gic-v4.1: Ensure L2 vPE table is allocated at RD level
irqchip/gic-v4.1: Set vpe_l1_base for all redistributors
irqchip/gic-v4.1: Fix programming of GICR_VPROPBASER_4_1_SIZE
genirq: Clarify that irq wake state is orthogonal to enable/disable
irqchip/gic-v3-its: Reference to its_invall_cmd descriptor when building INVALL
irqchip: Some Kconfig cleanup for C-SKY
irqchip/gic-v3: Only provision redistributors that are enabled in ACPI
Linus Torvalds [Sun, 9 Feb 2020 19:54:50 +0000 (11:54 -0800)]
Merge tag 'efi-urgent-2020-02-09' of git://git./linux/kernel/git/tip/tip
Pull EFI fix from Thomas Gleixner:
"A single fix for a EFI boot regression on X86 which was caused by the
recent rework of the EFI memory map parsing. On systems with invalid
memmap entries the cleanup function uses an value which cannot be
relied on in this stage. Use the actual EFI memmap entry instead"
* tag 'efi-urgent-2020-02-09' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
efi/x86: Fix boot regression on systems with invalid memmap entries
Linus Torvalds [Sun, 9 Feb 2020 01:24:41 +0000 (17:24 -0800)]
Merge tag 'scsi-misc' of git://git./linux/kernel/git/jejb/scsi
Pull misc SCSI fixes from James Bottomley:
"Five small patches, all in drivers or doc, which missed the initial
pull request.
The qla2xxx and megaraid_sas are actual fixes and the rest are
spelling and doc changes"
* tag 'scsi-misc' of git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi:
scsi: ufs: fix spelling mistake "initilized" -> "initialized"
scsi: pm80xx: fix spelling mistake "to" -> "too"
scsi: MAINTAINERS: ufs: remove pedrom.sousa@synopsys.com
scsi: megaraid_sas: fixup MSIx interrupt setup during resume
scsi: qla2xxx: Fix unbound NVME response length
Linus Torvalds [Sun, 9 Feb 2020 01:15:08 +0000 (17:15 -0800)]
Merge git://git./linux/kernel/git/netdev/net
Pull networking fixes from David Miller:
1) Unbalanced locking in mwifiex_process_country_ie, from Brian Norris.
2) Fix thermal zone registration in iwlwifi, from Andrei
Otcheretianski.
3) Fix double free_irq in sgi ioc3 eth, from Thomas Bogendoerfer.
4) Use after free in mptcp, from Florian Westphal.
5) Use after free in wireguard's root_remove_peer_lists, from Eric
Dumazet.
6) Properly access packets heads in bonding alb code, from Eric
Dumazet.
7) Fix data race in skb_queue_len(), from Qian Cai.
8) Fix regression in r8169 on some chips, from Heiner Kallweit.
9) Fix XDP program ref counting in hv_netvsc, from Haiyang Zhang.
10) Certain kinds of set link netlink operations can cause a NULL deref
in the ipv6 addrconf code. Fix from Eric Dumazet.
11) Don't cancel uninitialized work queue in drop monitor, from Ido
Schimmel.
* git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net: (84 commits)
net: thunderx: use proper interface type for RGMII
mt76: mt7615: fix max_nss in mt7615_eeprom_parse_hw_cap
bpf: Improve bucket_log calculation logic
selftests/bpf: Test freeing sockmap/sockhash with a socket in it
bpf, sockhash: Synchronize_rcu before free'ing map
bpf, sockmap: Don't sleep while holding RCU lock on tear-down
bpftool: Don't crash on missing xlated program instructions
bpf, sockmap: Check update requirements after locking
drop_monitor: Do not cancel uninitialized work item
mlxsw: spectrum_dpipe: Add missing error path
mlxsw: core: Add validation of hardware device types for MGPIR register
mlxsw: spectrum_router: Clear offload indication from IPv6 nexthops on abort
selftests: mlxsw: Add test cases for local table route replacement
mlxsw: spectrum_router: Prevent incorrect replacement of local table routes
net: dsa: microchip: enable module autoprobe
ipv6/addrconf: fix potential NULL deref in inet6_set_link_af()
dpaa_eth: support all modes with rate adapting PHYs
net: stmmac: update pci platform data to use phy_interface
net: stmmac: xgmac: fix missing IFF_MULTICAST checki in dwxgmac2_set_filter
net: stmmac: fix missing IFF_MULTICAST check in dwmac4_set_filter
...
Hans de Goede [Thu, 12 Dec 2019 14:09:14 +0000 (15:09 +0100)]
fs: Add VirtualBox guest shared folder (vboxsf) support
VirtualBox hosts can share folders with guests, this commit adds a
VFS driver implementing the Linux-guest side of this, allowing folders
exported by the host to be mounted under Linux.
This driver depends on the guest <-> host IPC functions exported by
the vboxguest driver.
Acked-by: Christoph Hellwig <hch@infradead.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
Linus Torvalds [Sat, 8 Feb 2020 22:28:26 +0000 (14:28 -0800)]
Merge tag 'powerpc-5.6-2' of git://git./linux/kernel/git/powerpc/linux
Pull powerpc fixes from Michael Ellerman:
- Fix an existing bug in our user access handling, exposed by one of
the bug fixes we merged this cycle.
- A fix for a boot hang on 32-bit with CONFIG_TRACE_IRQFLAGS and the
recently added CONFIG_VMAP_STACK.
Thanks to: Christophe Leroy, Guenter Roeck.
* tag 'powerpc-5.6-2' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux:
powerpc: Fix CONFIG_TRACE_IRQFLAGS with CONFIG_VMAP_STACK
powerpc/futex: Fix incorrect user access blocking
Linus Torvalds [Sat, 8 Feb 2020 22:19:39 +0000 (14:19 -0800)]
Fix up remaining devm_ioremap_nocache() in SGI IOC3 8250 UART driver
This is a merge error on my part - the driver was merged into mainline
by commit
c5951e7c8ee5 ("Merge tag 'mips_5.6' of git://../mips/linux")
over a week ago, but nobody apparently noticed that it didn't actually
build due to still having a reference to the devm_ioremap_nocache()
function, removed a few days earlier through commit
6a1000bd2703 ("Merge
tag 'ioremap-5.6' of git://../ioremap").
Apparently this didn't get any build testing anywhere. Not perhaps all
that surprising: it's restricted to 64-bit MIPS only, and only with the
new SGI_MFD_IOC3 support enabled.
I only noticed because the ioremap conflicts in the ARM SoC driver
update made me check there weren't any others hiding, and I found this
one.
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Linus Torvalds [Sat, 8 Feb 2020 22:17:27 +0000 (14:17 -0800)]
Merge tag 'armsoc-late' of git://git./linux/kernel/git/soc/soc
Pull ARM SoC late updates from Olof Johansson:
"This is some material that we picked up into our tree late, or that
had more complex dependencies on more than one topic branch that makes
sense to keep separately.
- TI support for secure accelerators and hwrng on OMAP4/5
- TI camera changes for dra7 and am437x and SGX improvement due to
better reset control support on am335x, am437x and dra7
- Davinci moves to proper clocksource on DM365, and regulator/audio
improvements for DM365 and DM644x eval boards"
* tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (32 commits)
ARM: dts: omap4-droid4: Enable hdq for droid4 ds250x 1-wire battery nvmem
ARM: dts: motorola-cpcap-mapphone: Configure calibration interrupt
ARM: dts: Configure interconnect target module for am437x sgx
ARM: dts: Configure sgx for dra7
ARM: dts: Configure rstctrl reset for am335x SGX
ARM: dts: dra7: Add ti-sysc node for VPE
ARM: dts: dra7: add vpe clkctrl node
ARM: dts: am43x-epos-evm: Add VPFE and OV2659 entries
ARM: dts: am437x-sk-evm: Add VPFE and OV2659 entries
ARM: dts: am43xx: add support for clkout1 clock
arm: dts: dra76-evm: Add CAL and OV5640 nodes
arm: dtsi: dra76x: Add CAL dtsi node
arm: dts: dra72-evm-common: Add entries for the CSI2 cameras
ARM: dts: DRA72: Add CAL dtsi node
ARM: dts: dra7-l4: Add ti-sysc node for CAM
ARM: OMAP: DRA7xx: Make CAM clock domain SWSUP only
ARM: dts: dra7: add cam clkctrl node
ARM: OMAP2+: Drop legacy platform data for omap4 des
ARM: OMAP2+: Drop legacy platform data for omap4 sham
ARM: OMAP2+: Drop legacy platform data for omap4 aes
...
Linus Torvalds [Sat, 8 Feb 2020 22:15:41 +0000 (14:15 -0800)]
Merge tag 'armsoc-defconfig' of git://git./linux/kernel/git/soc/soc
Pull ARM SoC defconfig updates from Olof Johansson:
"We keep this in a separate branch to avoid cross-branch conflicts, but
most of the material here is fairly boring -- some new drivers turned
on for hardware since they were merged, and some refreshed files due
to time having moved a lot of entries around"
* tag 'armsoc-defconfig' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (38 commits)
ARM: configs: at91: enable MMC_SDHCI_OF_AT91 and MICROCHIP_PIT64B
arm64: defconfig: Enable Broadcom's GENET Ethernet controller
ARM: multi_v7_defconfig: Enable devfreq thermal integration
ARM: exynos_defconfig: Enable devfreq thermal integration
ARM: multi_v7_defconfig: Enable NFS v4.1 and v4.2
ARM: exynos_defconfig: Enable NFS v4.1 and v4.2
arm64: defconfig: Enable Actions Semi specific drivers
arm64: defconfig: Enable Broadcom's STB PCIe controller
arm64: defconfig: Enable CONFIG_CLK_IMX8MP by default
ARM: configs: at91: enable config flags for sam9x60 SoC
ARM: configs: at91: use savedefconfig
arm64: defconfig: Enable tegra XUDC support
ARM: defconfig: gemini: Update defconfig
arm64: defconfig: enable CONFIG_ARM_QCOM_CPUFREQ_NVMEM
arm64: defconfig: enable CONFIG_QCOM_CPR
arm64: defconfig: Enable HFPLL
arm64: defconfig: Enable CRYPTO_DEV_FSL_CAAM
ARM: imx_v6_v7_defconfig: Select the TFP410 driver
ARM: imx_v6_v7_defconfig: Enable NFS_V4_1 and NFS_V4_2 support
arm64: defconfig: Enable ATH10K_SNOC
...
Linus Torvalds [Sat, 8 Feb 2020 22:04:19 +0000 (14:04 -0800)]
Merge tag 'armsoc-drivers' of git://git./linux/kernel/git/soc/soc
Pull ARM SoC-related driver updates from Olof Johansson:
"Various driver updates for platforms:
- Nvidia: Fuse support for Tegra194, continued memory controller
pieces for Tegra30
- NXP/FSL: Refactorings of QuickEngine drivers to support
ARM/ARM64/PPC
- NXP/FSL: i.MX8MP SoC driver pieces
- TI Keystone: ring accelerator driver
- Qualcomm: SCM driver cleanup/refactoring + support for new SoCs.
- Xilinx ZynqMP: feature checking interface for firmware. Mailbox
communication for power management
- Overall support patch set for cpuidle on more complex hierarchies
(PSCI-based)
and misc cleanups, refactorings of Marvell, TI, other platforms"
* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (166 commits)
drivers: soc: xilinx: Use mailbox IPI callback
dt-bindings: power: reset: xilinx: Add bindings for ipi mailbox
drivers: soc: ti: knav_qmss_queue: Pass lockdep expression to RCU lists
MAINTAINERS: Add brcmstb PCIe controller entry
soc/tegra: fuse: Unmap registers once they are not needed anymore
soc/tegra: fuse: Correct straps' address for older Tegra124 device trees
soc/tegra: fuse: Warn if straps are not ready
soc/tegra: fuse: Cache values of straps and Chip ID registers
memory: tegra30-emc: Correct error message for timed out auto calibration
memory: tegra30-emc: Firm up hardware programming sequence
memory: tegra30-emc: Firm up suspend/resume sequence
soc/tegra: regulators: Do nothing if voltage is unchanged
memory: tegra: Correct reset value of xusb_hostr
soc/tegra: fuse: Add APB DMA dependency for Tegra20
bus: tegra-aconnect: Remove PM_CLK dependency
dt-bindings: mediatek: add MT6765 power dt-bindings
soc: mediatek: cmdq: delete not used define
memory: tegra: Add support for the Tegra194 memory controller
memory: tegra: Only include support for enabled SoCs
memory: tegra: Support DVFS on Tegra186 and later
...
Linus Torvalds [Sat, 8 Feb 2020 21:58:44 +0000 (13:58 -0800)]
Merge tag 'armsoc-dt' of git://git./linux/kernel/git/soc/soc
Pull ARM Device-tree updates from Olof Johansson:
"New SoCs:
- Atmel/Microchip SAM9X60 (ARM926 SoC)
- OMAP 37xx gets split into AM3703/AM3715/DM3725, who are all
variants of it with different GPU/media IP configurations.
- ST stm32mp15 SoCs (1-2 Cortex-A7, CAN, GPU depending on SKU)
- ST Ericsson ab8505 (variant of ab8500) and db8520 (variant of
db8500)
- Unisoc SC9863A SoC (8x Cortex-A55 mobile chipset w/ GPU, modem)
- Qualcomm SC7180 (8-core 64bit SoC, unnamed CPU class)
New boards:
- Allwinner:
+ Emlid Neutis SoM (H3 variant)
+ Libre Computer ALL-H3-IT
+ PineH64 Model B
- Amlogic:
+ Libretech Amlogic GX PC (s905d and s912-based variants)
- Atmel/Microchip:
+ Kizboxmini, sam9x60 EK, sama5d27 Wireless SOM (wlsom1)
- Marvell:
+ Armada 385-based SolidRun Clearfog GTR
- NXP:
+ Gateworks GW59xx boards based on i.MX6/6Q/6QDL
+ Tolino Shine 3 eBook reader (i.MX6sl)
+ Embedded Artists COM (i.MX7ULP)
+ SolidRun CLearfog CX/ITX and HoneyComb (LX2160A-based systems)
+ Google Coral Edge TPU (i.MX8MQ)
- Rockchip:
+ Radxa Dalang Carrier (supports rk3288 and rk3399 SOMs)
+ Radxa Rock Pi N10 (RK3399Pro-based)
+ VMARC RK3399Pro SOM
- ST:
+ Reference boards for stm32mp15
- ST Ericsson:
+ Samsung Galaxy S III mini (GT-I8190)
+ HREF520 reference board for DB8520
- TI OMAP:
+ Gen1 Amazon Echo (OMAP3630-based)
- Qualcomm:
+ Inforce 6640 Single Board Computer (msm8996-based)
+ SC7180 IDP (SC7180-based)"
* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (623 commits)
dt-bindings: fix compilation error of the example in marvell,mmp3-hsic-phy.yaml
arm64: dts: ti: k3-am654-base-board: Add CSI2 OV5640 camera
arm64: dts: ti: k3-am65-main Add CAL node
arm64: dts: ti: k3-j721e-main: Add McASP nodes
arm64: dts: ti: k3-am654-main: Add McASP nodes
arm64: dts: ti: k3-j721e: DMA support
arm64: dts: ti: k3-j721e-main: Move secure proxy and smmu under main_navss
arm64: dts: ti: k3-j721e-main: Correct main NAVSS representation
arm64: dts: ti: k3-j721e: Correct the address for MAIN NAVSS
arm64: dts: ti: k3-am65: DMA support
arm64: dts: ti: k3-am65-main: Move secure proxy under cbass_main_navss
arm64: dts: ti: k3-am65-main: Correct main NAVSS representation
ARM: dts: aspeed: rainier: Add UCD90320 power sequencer
ARM: dts: aspeed: rainier: Switch PSUs to unknown version
arm64: dts: rockchip: Kill off "simple-panel" compatibles
ARM: dts: rockchip: Kill off "simple-panel" compatibles
arm64: dts: rockchip: rename dwmmc node names to mmc
ARM: dts: rockchip: rename dwmmc node names to mmc
arm64: dts: exynos: Rename Samsung and Exynos to lowercase
arm64: dts: uniphier: add reset-names to NAND controller node
...
Linus Torvalds [Sat, 8 Feb 2020 21:55:25 +0000 (13:55 -0800)]
Merge tag 'armsoc-soc' of git://git./linux/kernel/git/soc/soc
Pull ARM SoC platform updates from Olof Johansson:
"Most of these are smaller fixes that have accrued, and some continued
cleanup of OMAP platforms towards shared frameworks.
One new SoC from Atmel/Microchip: sam9x60"
* tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (35 commits)
ARM: OMAP2+: Fix undefined reference to omap_secure_init
ARM: s3c64xx: Drop unneeded select of TIMER_OF
ARM: exynos: Drop unneeded select of MIGHT_HAVE_CACHE_L2X0
ARM: s3c24xx: Switch to atomic pwm API in rx1950
ARM: OMAP2+: sleep43xx: Call secure suspend/resume handlers
ARM: OMAP2+: Use ARM SMC Calling Convention when OP-TEE is available
ARM: OMAP2+: Introduce check for OP-TEE in omap_secure_init()
ARM: OMAP2+: Add omap_secure_init callback hook for secure initialization
ARM: at91: Documentation: add sam9x60 product and datasheet
ARM: at91: pm: use of_device_id array to find the proper shdwc node
ARM: at91: pm: use SAM9X60 PMC's compatible
ARM: imx: only select ARM_ERRATA_814220 for ARMv7-A
ARM: zynq: use physical cpuid in zynq_slcr_cpu_stop/start
ARM: tegra: Use clk_m CPU on Tegra124 LP1 resume
ARM: tegra: Modify reshift divider during LP1
ARM: tegra: Enable PLLP bypass during Tegra124 LP1
ARM: samsung: Rename Samsung and Exynos to lowercase
ARM: exynos: Correct the help text for platform Kconfig option
ARM: bcm: Select ARM_AMBA for ARCH_BRCMSTB
ARM: brcmstb: Add debug UART entry for 7216
...