Peter Maydell [Fri, 4 Jan 2019 13:22:51 +0000 (13:22 +0000)]
Merge remote-tracking branch 'remotes/stefanha/tags/block-pull-request' into staging
Pull request
Bug fixes for the .dmg image file format.
# gpg: Signature made Fri 04 Jan 2019 11:21:18 GMT
# gpg: using RSA key
9CA4ABB381AB73C8
# gpg: Good signature from "Stefan Hajnoczi <stefanha@redhat.com>"
# gpg: aka "Stefan Hajnoczi <stefanha@gmail.com>"
# Primary key fingerprint: 8695 A8BF D3F9 7CDA AC35 775A 9CA4 ABB3 81AB 73C8
* remotes/stefanha/tags/block-pull-request:
dmg: don't skip zero chunk
dmg: use enumeration type instead of hard coding number
dmg: fix binary search
dmg: Fixing wrong dmg block type value for block terminator.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
yuchenlin [Thu, 3 Jan 2019 11:47:00 +0000 (19:47 +0800)]
dmg: don't skip zero chunk
The dmg file has many tables which describe: "start from sector XXX to
sector XXX, the compression method is XXX and where the compressed data
resides on".
Each sector in the expanded file should be covered by a table. The table
will describe the offset of compressed data (or raw depends on the type)
in the dmg.
For example:
[-----------The expanded file------------]
[---bzip table ---]/* zeros */[---zlib---]
^
| if we want to read this sector.
we will find bzip table which contains this sector, and get the
compressed data offset, read it from dmg, uncompress it, finally write to
expanded file.
If we skip zero chunk (table), some sector cannot find the table which
will cause search_chunk() return s->n_chunks, dmg_read_chunk() return -1
and finally causing dmg_co_preadv() return EIO.
See:
[-----------The expanded file------------]
[---bzip table ---]/* zeros */[---zlib---]
^
| if we want to read this sector.
Oops, we cannot find the table contains it...
In the original implementation, we don't have zero table. When we try to
read sector inside the zero chunk. We will get EIO, and skip reading.
After this patch, we treat zero chunk the same as ignore chunk, it will
directly write zero and avoid some sector may not find the table.
After this patch:
[-----------The expanded file------------]
[---bzip table ---][--zeros--][---zlib---]
Signed-off-by: yuchenlin <npes87184@gmail.com>
Reviewed-by: Julio Faracco <jcfaracco@gmail.com>
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Message-id:
20190103114700.9686-4-npes87184@gmail.com
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
yuchenlin [Thu, 3 Jan 2019 11:46:59 +0000 (19:46 +0800)]
dmg: use enumeration type instead of hard coding number
Signed-off-by: yuchenlin <npes87184@gmail.com>
Reviewed-by: Julio Faracco <jcfaracco@gmail.com>
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Message-id:
20190103114700.9686-3-npes87184@gmail.com
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
yuchenlin [Thu, 3 Jan 2019 11:46:58 +0000 (19:46 +0800)]
dmg: fix binary search
There is a possible hang in original binary search implementation. That is
if chunk1 = 4, chunk2 = 5, chunk3 = 4, and we go else case.
The chunk1 will be still 4, and so on.
Signed-off-by: yuchenlin <npes87184@gmail.com>
Message-id:
20190103114700.9686-2-npes87184@gmail.com
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Julio Faracco [Fri, 28 Dec 2018 14:50:55 +0000 (12:50 -0200)]
dmg: Fixing wrong dmg block type value for block terminator.
This is a trivial patch to fix a wrong value for block terminator.
The old value was 0x7fffffff which is wrong. It was not affecting the
code because QEMU dmg block is not handling block terminator right now.
Neverthless, it should be fixed.
Signed-off-by: Julio Faracco <jcfaracco@gmail.com>
Reviewed-by: yuchenlin <yuchenlin@synology.com>
Message-id:
20181228145055.18039-1-jcfaracco@gmail.com
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Peter Maydell [Fri, 4 Jan 2019 10:11:18 +0000 (10:11 +0000)]
Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-december-2018-v3' into staging
MIPS queue for December 2018 - v3
# gpg: Signature made Thu 03 Jan 2019 16:53:47 GMT
# gpg: using RSA key
D4972A8967F75A65
# gpg: Good signature from "Aleksandar Markovic <amarkovic@wavecomp.com>"
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 8526 FBF1 5DA3 811F 4A01 DD75 D497 2A89 67F7 5A65
* remotes/amarkovic/tags/mips-queue-december-2018-v3: (44 commits)
tests/tcg: mips: Test R5900 three-operand MADDU1
tests/tcg: mips: Test R5900 three-operand MADDU
tests/tcg: mips: Test R5900 three-operand MADD1
tests/tcg: mips: Test R5900 three-operand MADD
disas: nanoMIPS: Add a note on documentation
disas: nanoMIPS: Reorder declarations and definitions of gpr decoders
disas: nanoMIPS: Comment the decoder of 'gpr1' gpr encoding type
disas: nanoMIPS: Rename the decoder of 'gpr1' gpr encoding type
disas: nanoMIPS: Comment the decoder of 'gpr2.reg2' gpr encoding type
disas: nanoMIPS: Rename the decoder of 'gpr2.reg2' gpr encoding type
disas: nanoMIPS: Comment the decoder of 'gpr2.reg1' gpr encoding type
disas: nanoMIPS: Rename the decoder of 'gpr2.reg1' gpr encoding type
disas: nanoMIPS: Comment the decoder of 'gpr4.zero' gpr encoding type
disas: nanoMIPS: Rename the decoder of 'gpr4.zero' gpr encoding type
disas: nanoMIPS: Comment the decoder of 'gpr4' gpr encoding type
disas: nanoMIPS: Rename the decoder of 'gpr4' gpr encoding type
disas: nanoMIPS: Comment the decoder of 'gpr3.src.store' gpr encoding type
disas: nanoMIPS: Rename the decoder of 'gpr3.src.store' gpr encoding type
disas: nanoMIPS: Comment the decoder of 'gpr3' gpr encoding type
disas: nanoMIPS: Rename the decoder of 'gpr3' gpr encoding type
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Fredrik Noring [Thu, 27 Dec 2018 20:25:41 +0000 (21:25 +0100)]
tests/tcg: mips: Test R5900 three-operand MADDU1
Test R5900 three-operand MADDU1.
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Fredrik Noring <noring@nocrew.org>
Fredrik Noring [Thu, 27 Dec 2018 20:25:18 +0000 (21:25 +0100)]
tests/tcg: mips: Test R5900 three-operand MADDU
Test R5900 three-operand MADDU.
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Fredrik Noring <noring@nocrew.org>
Fredrik Noring [Thu, 27 Dec 2018 20:24:22 +0000 (21:24 +0100)]
tests/tcg: mips: Test R5900 three-operand MADD1
Test R5900 three-operand MADD1.
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Fredrik Noring <noring@nocrew.org>
Fredrik Noring [Thu, 27 Dec 2018 20:23:52 +0000 (21:23 +0100)]
tests/tcg: mips: Test R5900 three-operand MADD
Test R5900 three-operand MADD.
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Fredrik Noring <noring@nocrew.org>
Aleksandar Markovic [Wed, 26 Dec 2018 18:06:47 +0000 (19:06 +0100)]
disas: nanoMIPS: Add a note on documentation
Add "nanoMIPS32 Instruction Set Technical Reference Manual" as
a reference.
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Aleksandar Markovic [Wed, 26 Dec 2018 17:46:28 +0000 (18:46 +0100)]
disas: nanoMIPS: Reorder declarations and definitions of gpr decoders
Reorder declarations and definitions of gpr decoders by number of
input bits of corresponding encoding type.
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Aleksandar Markovic [Wed, 26 Dec 2018 17:41:23 +0000 (18:41 +0100)]
disas: nanoMIPS: Comment the decoder of 'gpr1' gpr encoding type
Comment the decoder of 'gpr1' gpr encoding type in nanoMIPS
disassembler.
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Aleksandar Markovic [Wed, 26 Dec 2018 17:35:52 +0000 (18:35 +0100)]
disas: nanoMIPS: Rename the decoder of 'gpr1' gpr encoding type
Rename the decoder of 'gpr1' gpr encoding type in nanoMIPS
disassembler.
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Aleksandar Markovic [Wed, 26 Dec 2018 13:42:13 +0000 (14:42 +0100)]
disas: nanoMIPS: Comment the decoder of 'gpr2.reg2' gpr encoding type
Comment the decoder of 'gpr2.reg2' gpr encoding type in nanoMIPS
disassembler.
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Aleksandar Markovic [Wed, 26 Dec 2018 13:40:17 +0000 (14:40 +0100)]
disas: nanoMIPS: Rename the decoder of 'gpr2.reg2' gpr encoding type
Rename the decoder of 'gpr2.reg2' gpr encoding type in nanoMIPS
disassembler.
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Aleksandar Markovic [Wed, 26 Dec 2018 13:38:15 +0000 (14:38 +0100)]
disas: nanoMIPS: Comment the decoder of 'gpr2.reg1' gpr encoding type
Comment the decoder of 'gpr2.reg1' gpr encoding type in nanoMIPS
disassembler.
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Aleksandar Markovic [Wed, 26 Dec 2018 13:30:39 +0000 (14:30 +0100)]
disas: nanoMIPS: Rename the decoder of 'gpr2.reg1' gpr encoding type
Rename the decoder of 'gpr2.reg1' gpr encoding type in nanoMIPS
disassembler.
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Aleksandar Markovic [Tue, 25 Dec 2018 14:55:09 +0000 (15:55 +0100)]
disas: nanoMIPS: Comment the decoder of 'gpr4.zero' gpr encoding type
Comment the decoder of 'gpr4.zero' gpr encoding type in nanoMIPS
disassembler.
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Aleksandar Markovic [Tue, 25 Dec 2018 14:46:00 +0000 (15:46 +0100)]
disas: nanoMIPS: Rename the decoder of 'gpr4.zero' gpr encoding type
Rename the decoder of 'gpr4.zero' gpr encoding type in nanoMIPS
disassembler.
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Aleksandar Markovic [Tue, 25 Dec 2018 14:42:58 +0000 (15:42 +0100)]
disas: nanoMIPS: Comment the decoder of 'gpr4' gpr encoding type
Comment the decoder of 'gpr4' gpr encoding type in nanoMIPS
disassembler.
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Aleksandar Markovic [Tue, 25 Dec 2018 14:30:07 +0000 (15:30 +0100)]
disas: nanoMIPS: Rename the decoder of 'gpr4' gpr encoding type
Rename the decoder of 'gpr4' gpr encoding type in nanoMIPS
disassembler.
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Aleksandar Markovic [Tue, 25 Dec 2018 14:18:18 +0000 (15:18 +0100)]
disas: nanoMIPS: Comment the decoder of 'gpr3.src.store' gpr encoding type
Comment the decoder of 'gpr3.src.store' gpr encoding type in nanoMIPS
disassembler.
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Aleksandar Markovic [Tue, 25 Dec 2018 14:09:49 +0000 (15:09 +0100)]
disas: nanoMIPS: Rename the decoder of 'gpr3.src.store' gpr encoding type
Rename the decoder of 'gpr3.src.store' gpr encoding type in nanoMIPS
disassembler.
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Aleksandar Markovic [Tue, 25 Dec 2018 14:06:15 +0000 (15:06 +0100)]
disas: nanoMIPS: Comment the decoder of 'gpr3' gpr encoding type
Comment the decoder of 'gpr3' gpr encoding type in nanoMIPS
disassembler.
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Aleksandar Markovic [Tue, 25 Dec 2018 13:19:12 +0000 (14:19 +0100)]
disas: nanoMIPS: Rename the decoder of 'gpr3' gpr encoding type
Rename the decoder of 'gpr3' gpr encoding type in nanoMIPS
disassembler.
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Aleksandar Markovic [Mon, 24 Dec 2018 15:18:53 +0000 (16:18 +0100)]
disas: nanoMIPS: Fix order of more invocations
Fix order of extraction function invocations so that extraction
goes from MSB side to LSB side of the given instruction coding
content. This is desireable because of consistency and easier
visual spotting of errors.
After this patch, all such invocations should be in the desired
order.
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Aleksandar Markovic [Mon, 24 Dec 2018 14:36:04 +0000 (15:36 +0100)]
disas: nanoMIPS: Name more functions in a more descriptive way
Rename more functions that have names that are hard to understand.
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Aleksandar Markovic [Tue, 18 Dec 2018 03:19:28 +0000 (04:19 +0100)]
disas: nanoMIPS: Fix an FP-related misnomer 3
Rename NMD::extract_ft_20_19_18_17_16(uint64 instruction) to
NMD::extract_ft_25_24_23_22_21(uint64 instruction).
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Aleksandar Markovic [Tue, 18 Dec 2018 03:16:15 +0000 (04:16 +0100)]
disas: nanoMIPS: Fix an FP-related misnomer 2
Rename NMD::extract_fs_15_14_13_12_11(uint64 instruction) to
NMD::extract_fs_20_19_18_17_16(uint64 instruction).
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Aleksandar Markovic [Tue, 18 Dec 2018 03:12:53 +0000 (04:12 +0100)]
disas: nanoMIPS: Fix an FP-related misnomer 1
Rename NMD::extract_fd_10_9_8_7_6(uint64 instruction) to
NMD::extract_fd_15_14_13_12_11(uint64 instruction).
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Aleksandar Markovic [Mon, 17 Dec 2018 14:23:35 +0000 (15:23 +0100)]
disas: nanoMIPS: Name some functions in a more descriptive way
Rename some functions that have names that are hard to understand.
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Aleksandar Markovic [Mon, 17 Dec 2018 02:01:16 +0000 (03:01 +0100)]
disas: nanoMIPS: Fix order of some invocations
Fix order of extraction function invocations so that extraction
goes from MSB side to LSB side of the given instruction coding
content. This is desireable because of consistency and easier
visual spotting of errors.
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Aleksandar Markovic [Mon, 17 Dec 2018 00:44:04 +0000 (01:44 +0100)]
disas: nanoMIPS: Fix a function misnomer
Fix wrong function name. The convention in these files is that names of
extraction functions should reflect bit patterns they are extracting.
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Aleksandar Markovic [Mon, 17 Dec 2018 00:38:33 +0000 (01:38 +0100)]
disas: nanoMIPS: Remove functions that are not used
Some functions were not used at all. Compiler doesn't complain
since they are class memebers. Remove them - no future usage is
planned.
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Aleksandar Markovic [Mon, 17 Dec 2018 00:28:44 +0000 (01:28 +0100)]
disas: nanoMIPS: Fix preamble text in nanomips.* files
Fix several mistakes in preambles of nanomips disassembler source
files.
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Stefan Weil [Thu, 27 Dec 2018 16:56:04 +0000 (17:56 +0100)]
disas: nanoMIPS: Fix types and format strings
Use POSIX types and format strings.
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Stefan Weil <sw@weilnetz.de>
Fredrik Noring [Thu, 27 Dec 2018 19:29:14 +0000 (20:29 +0100)]
target/mips: Support R5900 three-operand MADD1 and MADDU1 instructions
The three-operand MADD and MADDU are specific to R5900 cores.
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Fredrik Noring <noring@nocrew.org>
Philippe Mathieu-Daudé [Thu, 27 Dec 2018 18:00:44 +0000 (19:00 +0100)]
target/mips: Support R5900 three-operand MADD and MADDU instructions
The three-operand MADD and MADDU are specific to Sony R5900 core,
and Toshiba TX19/TX39/TX79 cores as well.
The "32-Bit TX System RISC TX39 Family Architecture manual"
is available at https://wiki.qemu.org/File:DSAE0022432.pdf
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Philippe Mathieu-Daudé<f4bug@amsat.org>
Signed-off-by: Fredrik Noring <noring@nocrew.org>
Tested-by: Fredrik Noring <noring@nocrew.org>
Aleksandar Markovic [Mon, 31 Dec 2018 12:14:56 +0000 (13:14 +0100)]
target/mips: MXU: Add handler for an align instruction
Add translation handler for S32ALNI MXU instruction.
Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Aleksandar Markovic [Mon, 31 Dec 2018 12:14:34 +0000 (13:14 +0100)]
target/mips: MXU: Add handlers for max/min instructions
Add translation handlers for six max/min MXU instructions.
Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Aleksandar Markovic [Mon, 31 Dec 2018 12:14:13 +0000 (13:14 +0100)]
target/mips: MXU: Add handlers for logic instructions
Add translation handlers for four logic MXU instructions.
It should be noted that there is an error in MXU documentation (dated
June 2017) regarding opcodes for this group of instructions. This was
confirmed by running tests on hardware, and also by looking up other
related public source trees (binutils, Android NDK). In initial MXU
patches to QEMU, opcodes for MXU logic instructions were created to
be in accordance with the MXU documentation, therefore the error from
was propagated. This patch corrects that, changing the involved code.
Besides that, as MXU was designed and implemented only for 32-bit
CPUs, corresponding preprosessor conditions were added around MXU
code, which allows more flexible implementation of MXU handlers.
Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Aleksandar Markovic [Thu, 27 Dec 2018 16:25:00 +0000 (17:25 +0100)]
target/mips: MXU: Improve the comment containing MXU overview
Improve textual description of MXU extension. These are mostly
comment formatting changes.
Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Aleksandar Markovic [Thu, 27 Dec 2018 16:20:38 +0000 (17:20 +0100)]
target/mips: MXU: Add generic naming for optn2 constants
Add generic naming involving generig suffixes OPTN0, OPTN1, OPTN2,
OPTN3 for four optn2 constants. Existing suffixes WW, LW, HW, XW
are not quite appropriate for some instructions using optn2.
Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Aleksandar Markovic [Thu, 27 Dec 2018 16:17:35 +0000 (17:17 +0100)]
target/mips: MXU: Add missing opcodes/decoding for LX* instructions
Add missing opcodes and decoding engine for LXB, LXH, LXW, LXBU,
and LXHU instructions. They were for some reason forgotten in
previous commits. The MXU opcode list and decoding engine should
be now complete.
Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Paul Burton [Thu, 27 Dec 2018 15:32:11 +0000 (16:32 +0100)]
atomics: Set ATOMIC_REG_SIZE=8 for MIPS n32
ATOMIC_REG_SIZE is currently defined as the default sizeof(void *) for
all MIPS host builds, including those using the n32 ABI. n32 is the
MIPS64 ILP32 ABI and as such tcg/mips/tcg-target.h defines
TCG_TARGET_REG_BITS as 64 for n32 builds. If we attempt to build QEMU
for an n32 host with support for a 64b target architecture then
TCG_OVERSIZED_GUEST is 0 and accel/tcg/cputlb.c attempts to use
atomic_* functions. This fails because ATOMIC_REG_SIZE is 4, causing
the calls to QEMU_BUILD_BUG_ON(sizeof(*ptr) > ATOMIC_REG_SIZE) in the
various atomic_* functions to generate errors.
Fix this by defining ATOMIC_REG_SIZE as 8 for all MIPS64 builds, which
will cover both n32 (ILP32) & n64 (LP64) ABIs in much the same was as
we already do for x86_64/x32.
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Paul Burton <pburton@wavecomp.com>
Aleksandar Markovic [Wed, 26 Dec 2018 16:46:56 +0000 (17:46 +0100)]
MAINTAINERS: Add Aleksandar Rikalo as a reviewer for MIPS content
Add Aleksandar Rikalo as a reviewer for MIPS content. Aleksandar
brings to us more than six years of experience in working on a variety
of development tools for MIPS architectures, and will greatly help
QEMU community understand and support intricacies of MIPS better.
Acked-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Aleksandar Markovic [Mon, 17 Dec 2018 16:50:09 +0000 (17:50 +0100)]
MAINTAINERS: target/mips: Reorder items alphabetically
Reorder items alphabetically for better visibility.
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Aleksandar Markovic [Mon, 17 Dec 2018 16:43:11 +0000 (17:43 +0100)]
MAINTAINERS: target/mips: Add filter for mips in email subjects
Add ability to redirect mails (sent to qemu-devel) containing
"mips" in the subject line to MIPS maintainers and reviewers.
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Aleksandar Markovic [Mon, 17 Dec 2018 16:30:51 +0000 (17:30 +0100)]
MAINTAINERS: target/mips: Add MIPS files under default-configs directory
Add following files as maintained within the main MIPS target
section in MAINTAINERS:
default-configs/mips64el-linux-user.mak
default-configs/mips64-linux-user.mak
default-configs/mipsn32el-linux-user.mak
default-configs/mipsn32-linux-user.mak
default-configs/mipsel-linux-user.mak
default-configs/mips-linux-user.mak
default-configs/mips64el-softmmu.mak
default-configs/mips64-softmmu.mak
default-configs/mipsel-softmmu.mak
default-configs/mips-softmmu.mak
default-configs/mips-softmmu-common.mak
Future nanoMIPS user mode will also have its .mak file, and
because of that "*mips*" was used instead of "mips*" as a
shorthand in the new item in MAINTAINERS.
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Peter Maydell [Thu, 3 Jan 2019 13:26:30 +0000 (13:26 +0000)]
Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-3.2-part1' into staging
RISC-V Changes for 3.2, Part 1
This pull request contains the first set of RISC-V patches I'd like to
target for the 3.2 development cycle. It's really just a collection of
bug fixes with one major new feature: PCIe can now be attached to RISC-V
guests.
This has passed my usual test of booting the latest Linux RC into a
Fedora disk image on the virt machine.
# gpg: Signature made Fri 21 Dec 2018 16:01:29 GMT
# gpg: using RSA key
EF4CA1502CCBAB41
# gpg: Good signature from "Palmer Dabbelt <palmer@dabbelt.com>"
# gpg: aka "Palmer Dabbelt <palmer@sifive.com>"
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 00CE 76D1 8349 60DF CE88 6DF8 EF4C A150 2CCB AB41
* remotes/palmer/tags/riscv-for-master-3.2-part1:
MAINTAINERS: Mark RISC-V as Supported
riscv/cpu: use device_class_set_parent_realize
target/riscv/pmp.c: Fix pmp_decode_napot()
sifive_uart: Implement interrupt pending register
RISC-V: Enable second UART on sifive_e and sifive_u
RISC-V: Fix PLIC pending bitfield reads
RISC-V: Fix CLINT timecmp low 32-bit writes
RISC-V: Add hartid and \n to interrupt logging
sifive_u: Set 'clock-frequency' DT property for SiFive UART
sifive_u: Add clock DT node for GEM ethernet
riscv: Enable VGA and PCIE_VGA
hw/riscv/virt: Connect the gpex PCIe
hw/riscv/virt: Adjust memory layout spacing
hw/riscv/virt: Increase the number of interrupts
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Peter Maydell [Thu, 3 Jan 2019 10:42:21 +0000 (10:42 +0000)]
Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-
20181226' into staging
Host support for riscv64.
Dead code elimination pass.
Register allocation improvements.
# gpg: Signature made Tue 25 Dec 2018 20:52:34 GMT
# gpg: using RSA key
64DF38E8AF7E215F
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>"
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F
* remotes/rth/tags/pull-tcg-
20181226: (42 commits)
tcg: Improve call argument loading
tcg: Record register preferences during liveness
tcg: Add TCG_OPF_BB_EXIT
tcg: Split out more subroutines from liveness_pass_1
tcg: Rename and adjust liveness_pass_1 helpers
tcg: Reindent parts of liveness_pass_1
tcg: Dump register preference info with liveness
tcg: Improve register allocation for matching constraints
tcg: Add output_pref to TCGOp
tcg: Add preferred_reg argument to tcg_reg_alloc_do_movi
tcg: Add preferred_reg argument to temp_sync
tcg: Add preferred_reg argument to temp_load
tcg: Add preferred_reg argument to tcg_reg_alloc
tcg: Add reachable_code_pass
tcg: Reference count labels
tcg: Add TCG_CALL_NO_RETURN
tcg: Renumber TCG_CALL_* flags
linux-user: Add safe_syscall for riscv64 host
disas/microblaze: Remove unused REG_SP macro
configure: Add support for building RISC-V host
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Tue, 11 Dec 2018 16:25:02 +0000 (10:25 -0600)]
tcg: Improve call argument loading
Free the argument register only after we have verified that the
temporary is not already in that register. This case is likely
now that we are back propagating the preferred register.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Tue, 27 Nov 2018 20:45:26 +0000 (12:45 -0800)]
tcg: Record register preferences during liveness
With these preferences, we can arrange for function call arguments to
be computed into the proper registers instead of requiring extra moves.
Reviewed-by: Emilio G. Cota <cota@braap.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Tue, 27 Nov 2018 21:45:08 +0000 (13:45 -0800)]
tcg: Add TCG_OPF_BB_EXIT
Use this to notice the opcodes that exit the TB, which implies
that local temps are really dead and need not be synced.
Previously we so marked the true end of the TB, but that was
immediately overwritten by the la_bb_end invoked by any
TCG_OPF_BB_END opcode, like exit_tb.
Reviewed-by: Emilio G. Cota <cota@braap.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Tue, 27 Nov 2018 22:00:35 +0000 (14:00 -0800)]
tcg: Split out more subroutines from liveness_pass_1
Reviewed-by: Emilio G. Cota <cota@braap.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Tue, 27 Nov 2018 21:37:24 +0000 (13:37 -0800)]
tcg: Rename and adjust liveness_pass_1 helpers
No need for a "tcg_" prefix for a static function; we already
have another "la_" prefix for indicating liveness analysis.
Pass in nb_globals and nb_temps, as we will already have them
in registers for other loops within the parent function.
Reviewed-by: Emilio G. Cota <cota@braap.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Tue, 27 Nov 2018 21:32:33 +0000 (13:32 -0800)]
tcg: Reindent parts of liveness_pass_1
There are two blocks of the form
if (foo) {
stuff1;
goto bar;
} else {
baz:
stuff2;
}
which have unnecessary and confusing indentation.
Remove the else and unindent stuff2.
Reviewed-by: Emilio G. Cota <cota@braap.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Tue, 27 Nov 2018 20:46:00 +0000 (12:46 -0800)]
tcg: Dump register preference info with liveness
Reviewed-by: Emilio G. Cota <cota@braap.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Wed, 28 Nov 2018 04:21:31 +0000 (20:21 -0800)]
tcg: Improve register allocation for matching constraints
Try harder to honor the output_pref. When we're forced to allocate
a second register for the input, it does not need to use the input
constraint; that will be honored by the register we allocate for the
output and a move is already required.
Reviewed-by: Emilio G. Cota <cota@braap.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Tue, 27 Nov 2018 15:44:51 +0000 (07:44 -0800)]
tcg: Add output_pref to TCGOp
Allocate storage for, but do not yet fill in, per-opcode
preferences for the output operands. Pass it in to the
register allocation routines for output operands.
Reviewed-by: Emilio G. Cota <cota@braap.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Tue, 27 Nov 2018 23:39:21 +0000 (15:39 -0800)]
tcg: Add preferred_reg argument to tcg_reg_alloc_do_movi
Pass this through to temp_sync.
Reviewed-by: Emilio G. Cota <cota@braap.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Tue, 27 Nov 2018 23:35:04 +0000 (15:35 -0800)]
tcg: Add preferred_reg argument to temp_sync
Pass this through to tcg_reg_alloc.
Reviewed-by: Emilio G. Cota <cota@braap.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Tue, 27 Nov 2018 15:48:06 +0000 (07:48 -0800)]
tcg: Add preferred_reg argument to temp_load
Pass this through to tcg_reg_alloc.
Reviewed-by: Emilio G. Cota <cota@braap.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Tue, 27 Nov 2018 15:16:21 +0000 (07:16 -0800)]
tcg: Add preferred_reg argument to tcg_reg_alloc
This new argument will aid register allocation by indicating how
the temporary will be used in future. If the preference cannot
be satisfied, fall back to the constraints of the current insn.
Short circuit the preference when it cannot be satisfied or if
it does not further constrain the operation.
With an eye toward optimizing function call sequences, optimize
for the preferred_reg set containing a single register.
For the moment, all users pass 0 for preference.
Reviewed-by: Emilio G. Cota <cota@braap.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Mon, 26 Nov 2018 22:28:28 +0000 (14:28 -0800)]
tcg: Add reachable_code_pass
Delete trivially dead code that follows unconditional branches and
noreturn helpers. These can occur either via optimization or via
the structure of a target's translator following an exception.
Reviewed-by: Emilio G. Cota <cota@braap.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Mon, 26 Nov 2018 20:47:28 +0000 (12:47 -0800)]
tcg: Reference count labels
Increment when adding branches, and decrement when removing them.
Reviewed-by: Emilio G. Cota <cota@braap.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Mon, 26 Nov 2018 19:32:38 +0000 (11:32 -0800)]
tcg: Add TCG_CALL_NO_RETURN
Remember which helpers have been marked noreturn.
Reviewed-by: Emilio G. Cota <cota@braap.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Mon, 26 Nov 2018 18:37:34 +0000 (10:37 -0800)]
tcg: Renumber TCG_CALL_* flags
Previously, the low 4 bits were used for TCG_CALL_TYPE_MASK,
which was removed in
6a18ae2d2947532d5c26439548afa0481c4529f9.
Reviewed-by: Emilio G. Cota <cota@braap.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Thu, 20 Dec 2018 20:10:15 +0000 (12:10 -0800)]
linux-user: Add safe_syscall for riscv64 host
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Fri, 30 Nov 2018 00:49:54 +0000 (16:49 -0800)]
disas/microblaze: Remove unused REG_SP macro
This causes a build error with debian sid, riscv64 host:
disas/microblaze.c:179: error: "REG_SP" redefined [-Werror]
#define REG_SP 1 /* stack pointer */
In file included from /usr/include/signal.h:306,
from include/qemu/osdep.h:101,
from disas/microblaze.c:36:
/usr/include/riscv64-linux-gnu/sys/ucontext.h:36: note: this is the location of the previous definition
# define REG_SP 2
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Alistair Francis [Wed, 19 Dec 2018 19:20:19 +0000 (19:20 +0000)]
configure: Add support for building RISC-V host
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Michael Clark <mjc@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
52160afacecc5b109dc43a412fa3e74ddd6277fb.
1545246859.git.alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Alistair Francis [Wed, 19 Dec 2018 19:20:09 +0000 (19:20 +0000)]
disas: Add RISC-V support
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Michael Clark <mjc@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
caa478c8987d6042434bb9582017cdf0ea192208.
1545246859.git.alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Alistair Francis [Wed, 19 Dec 2018 19:19:59 +0000 (19:19 +0000)]
tcg: Add RISC-V cpu signal handler
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Michael Clark <mjc@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
c445175310fa836b61fd862a55628907f0093194.
1545246859.git.alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Alistair Francis [Wed, 19 Dec 2018 19:19:49 +0000 (19:19 +0000)]
tcg/riscv: Add the target init code
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Michael Clark <mjc@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
dd6e439ab81883974b8fd91f904f6de26ab5d697.
1545246859.git.alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Alistair Francis [Wed, 19 Dec 2018 19:19:39 +0000 (19:19 +0000)]
tcg/riscv: Add the prologue generation and register the JIT
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Michael Clark <mjc@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
c4d023127967a0217d8d1eabdf5de6c0e8f8c228.
1545246859.git.alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Alistair Francis [Wed, 19 Dec 2018 19:19:29 +0000 (19:19 +0000)]
tcg/riscv: Add the out op decoder
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Michael Clark <mjc@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
7c47f00cb4a9a777120456e0704b4076a5d943ab.
1545246859.git.alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Alistair Francis [Wed, 19 Dec 2018 19:19:20 +0000 (19:19 +0000)]
tcg/riscv: Add direct load and store instructions
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Michael Clark <mjc@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
2e047a95c39c007c66cda024c095e29b0ac4c43e.
1545246859.git.alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Alistair Francis [Wed, 19 Dec 2018 19:19:11 +0000 (19:19 +0000)]
tcg/riscv: Add slowpath load and store instructions
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Michael Clark <mjc@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
1a0a7e8f3347764f212c5efa5c07c9be17efdec6.
1545246859.git.alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Alistair Francis [Wed, 19 Dec 2018 19:19:00 +0000 (19:19 +0000)]
tcg/riscv: Add branch and jump instructions
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Michael Clark <mjc@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
c356657e627168d89cb5b012b7e21e4efbbe83f3.
1545246859.git.alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Alistair Francis [Wed, 19 Dec 2018 19:18:49 +0000 (19:18 +0000)]
tcg/riscv: Add the add2 and sub2 instructions
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
5665a57809e32b35775e8e98fdab898853af37b8.
1545246859.git.alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Alistair Francis [Wed, 19 Dec 2018 19:18:39 +0000 (19:18 +0000)]
tcg/riscv: Add the out load and store instructions
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Michael Clark <mjc@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
d5d88ff29163788938368bbdbd18815d59cef6a0.
1545246859.git.alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Alistair Francis [Wed, 19 Dec 2018 19:18:28 +0000 (19:18 +0000)]
tcg/riscv: Add the extract instructions
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Michael Clark <mjc@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
c4d2afba46efefa9388cf3205fcedbb9a5fa411f.
1545246859.git.alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Alistair Francis [Wed, 19 Dec 2018 19:18:17 +0000 (19:18 +0000)]
tcg/riscv: Add the mov and movi instruction
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Michael Clark <mjc@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
bd6a45c73a67b77ddaa2fe590a6bb8ee422b9683.
1545246859.git.alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Alistair Francis [Wed, 19 Dec 2018 19:18:06 +0000 (19:18 +0000)]
tcg/riscv: Add the relocation functions
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Michael Clark <mjc@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
6ac4f4b0d5ea93cb0ee9a3b8b47ee9f7b3711494.
1545246859.git.alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Alistair Francis [Wed, 19 Dec 2018 19:17:55 +0000 (19:17 +0000)]
tcg/riscv: Add the instruction emitters
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Michael Clark <mjc@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
c740aca183675625bb9cf3ce7b9e8b9d431ca694.
1545246859.git.alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Alistair Francis [Wed, 19 Dec 2018 19:17:43 +0000 (19:17 +0000)]
tcg/riscv: Add the immediate encoders
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Michael Clark <mjc@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
d54dc56303fd1b0d7ed53869de2dbb59b111c7ca.
1545246859.git.alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Alistair Francis [Wed, 19 Dec 2018 19:17:32 +0000 (19:17 +0000)]
tcg/riscv: Add support for the constraints
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Michael Clark <mjc@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
dba7315e4e20e879933f72d47ccf98f1cc612b8a.
1545246859.git.alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Alistair Francis [Wed, 19 Dec 2018 19:17:20 +0000 (19:17 +0000)]
tcg/riscv: Add the tcg target registers
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Michael Clark <mjc@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
6e43abaa64361d57b9bc9439820d0e7701f2d47e.
1545246859.git.alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Alistair Francis [Wed, 19 Dec 2018 19:17:07 +0000 (19:17 +0000)]
tcg/riscv: Add the tcg-target.h file
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Michael Clark <mjc@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
a135ee1a88cd7bd08993a519d4d654da27785254.
1545246859.git.alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Alistair Francis [Wed, 19 Dec 2018 19:16:52 +0000 (19:16 +0000)]
exec: Add RISC-V GCC poison macro
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Michael Clark <mjc@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
00d02e34f10b87fd61f8dc69ac93d1eb63df949c.
1545246859.git.alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Alistair Francis [Wed, 19 Dec 2018 19:16:41 +0000 (19:16 +0000)]
linux-user: Add host dependency for RISC-V 64-bit
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Michael Clark <mjc@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
9d777f619840a8dd8e4f3834dcfc3bd28e052ccd.
1545246859.git.alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Alistair Francis [Wed, 19 Dec 2018 19:16:31 +0000 (19:16 +0000)]
linux-user: Add host dependency for RISC-V 32-bit
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Michael Clark <mjc@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
76f8f9383a766dbcade883e897dec8cfef669799.
1545246859.git.alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Alistair Francis [Wed, 19 Dec 2018 19:16:22 +0000 (19:16 +0000)]
elf.h: Add the RISCV ELF magic numbers
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Michael Clark <mjc@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
02fc0b3a733f5f08eb396bee5afd3d327941f0c9.
1545246859.git.alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Peter Maydell [Sat, 22 Dec 2018 11:25:31 +0000 (11:25 +0000)]
Merge remote-tracking branch 'remotes/marcel/tags/rdma-pull-request' into staging
RDMA queue
* Add support for RDMA MAD
* Various fixes for the pvrdma backend
# gpg: Signature made Sat 22 Dec 2018 09:36:36 GMT
# gpg: using RSA key
36D4C0F0CF2FE46D
# gpg: Good signature from "Marcel Apfelbaum <marcel.apfelbaum@zoho.com>"
# gpg: aka "Marcel Apfelbaum <marcel@redhat.com>"
# gpg: aka "Marcel Apfelbaum <marcel.apfelbaum@gmail.com>"
# gpg: WARNING: This key is not certified with sufficiently trusted signatures!
# gpg: It is not certain that the signature belongs to the owner.
# Primary key fingerprint: B1C6 3A57 F92E 08F2 640F 31F5 36D4 C0F0 CF2F E46D
* remotes/marcel/tags/rdma-pull-request: (31 commits)
pvrdma: check return value from pvrdma_idx_ring_has_ routines
rdma: remove unused VENDOR_ERR_NO_SGE macro
pvrdma: release ring object in case of an error
pvrdma: check number of pages when creating rings
pvrdma: add uar_read routine
rdma: check num_sge does not exceed MAX_SGE
pvrdma: release device resources in case of an error
docs: Update pvrdma device documentation
hw/rdma: Do not call rdma_backend_del_gid on an empty gid
hw/rdma: Do not use bitmap_zero_extend to free bitmap
hw/pvrdma: Clean device's resource when system is shutdown
vl: Introduce shutdown_notifiers
hw/rdma: Remove unneeded code that handles more that one port
hw/pvrdma: Fill error code in command's response
hw/pvrdma: Fill all CQE fields
hw/pvrdma: Make device state depend on Ethernet function state
hw/rdma: Initialize node_guid from vmxnet3 mac address
hw/pvrdma: Make sure PCI function 0 is vmxnet3
vmxnet3: Move some definitions to header file
hw/pvrdma: Add support to allow guest to configure GID table
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Prasad J Pandit [Wed, 12 Dec 2018 19:30:39 +0000 (01:00 +0530)]
pvrdma: check return value from pvrdma_idx_ring_has_ routines
pvrdma_idx_ring_has_[data/space] routines also return invalid
index PVRDMA_INVALID_IDX[=-1], if ring has no data/space. Check
return value from these routines to avoid plausible infinite loops.
Reported-by: Li Qiang <liq3ea@163.com>
Signed-off-by: Prasad J Pandit <pjp@fedoraproject.org>
Reviewed-by: Yuval Shaia <yuval.shaia@oracle.com>
Signed-off-by: Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
Prasad J Pandit [Wed, 12 Dec 2018 19:30:38 +0000 (01:00 +0530)]
rdma: remove unused VENDOR_ERR_NO_SGE macro
With commit
4481985c (rdma: check num_sge does not exceed MAX_SGE)
macro VENDOR_ERR_NO_SGE is no longer in use - delete it.
Signed-off-by: Prasad J Pandit <pjp@fedoraproject.org>
Reviewed-by: Yuval Shaia <yuval.shaia@oracle.com>
Signed-off-by: Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
Prasad J Pandit [Wed, 12 Dec 2018 19:30:37 +0000 (01:00 +0530)]
pvrdma: release ring object in case of an error
create_cq and create_qp routines allocate ring object, but it's
not released in case of an error, leading to memory leakage.
Reported-by: Li Qiang <liq3ea@163.com>
Signed-off-by: Prasad J Pandit <pjp@fedoraproject.org>
Reviewed-by: Yuval Shaia <yuval.shaia@oracle.com>
Signed-off-by: Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
Prasad J Pandit [Wed, 12 Dec 2018 19:30:36 +0000 (01:00 +0530)]
pvrdma: check number of pages when creating rings
When creating CQ/QP rings, an object can have up to
PVRDMA_MAX_FAST_REG_PAGES 8 pages. Check 'npages' parameter
to avoid excessive memory allocation or a null dereference.
Reported-by: Li Qiang <liq3ea@163.com>
Signed-off-by: Prasad J Pandit <pjp@fedoraproject.org>
Reviewed-by: Yuval Shaia <yuval.shaia@oracle.com>
Signed-off-by: Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
Prasad J Pandit [Wed, 12 Dec 2018 19:30:35 +0000 (01:00 +0530)]
pvrdma: add uar_read routine
Define skeleton 'uar_read' routine. Avoid NULL dereference.
Reported-by: Li Qiang <liq3ea@163.com>
Signed-off-by: Prasad J Pandit <pjp@fedoraproject.org>
Reviewed-by: Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
Signed-off-by: Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
projects / qemu.git / log