Arnd Bergmann [Mon, 20 Dec 2021 14:55:51 +0000 (15:55 +0100)]
Merge tag 'ti-k3-dt-for-v5.17' of git://git./linux/kernel/git/ti/linux into arm/dt
Devicetree changes for TI K3 platforms for v5.17 merge window:
* New Platforms:
- J721s2 SoC, SoM and Common Processor Board support
* New features:
- CAN support on AM64 EVM and SK
- TimeSync Router on AM64
* Fixes:
- Correct d-cache-sets info on J7200
- Fix L2 cache-sets value for J721e/J7200/AM64
- Fixes for dtbs_check warnings wrt serdes_ln_ctrl node on J721e/J7200
- Disable McASP on IoT2050 board to fix dtbs_check warnings
* tag 'ti-k3-dt-for-v5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/ti/linux:
arch: arm64: ti: Add support J721S2 Common Processor Board
arm64: dts: ti: Add initial support for J721S2 System on Module
arm64: dts: ti: Add initial support for J721S2 SoC
dt-bindings: pinctrl: k3: Introduce pinmux definitions for J721S2
dt-bindings: arm: ti: Add bindings for J721s2 SoC
arm64: dts: ti: iot2050: Disable mcasp nodes at dtsi level
arm64: dts: ti: k3-am642-evm/sk: Add support for main domain mcan nodes in EVM and disable them on SK
arm64: dts: ti: k3-am64-main: Add support for MCAN
arm64: dts: ti: k3-j721e-common-proc-board: Add support for mcu and main mcan nodes
arm64: dts: ti: k3-j721e: Add support for MCAN nodes
arm64: dts: ti: am654-base-board/am65-iot2050-common: Disable mcan nodes
arm64: dts: ti: k3-am65-mcu: Add Support for MCAN
arm64: dts: ti: k3-am64-main: add timesync router node
arm64: dts: ti: k3-j7200: Correct the d-cache-sets info
arm64: dts: ti: k3-j721e: Fix the L2 cache sets
arm64: dts: ti: k3-j7200: Fix the L2 cache sets
arm64: dts: ti: k3-am642: Fix the L2 cache sets
arm64: dts: ti: j721e-main: Fix 'dtbs_check' in serdes_ln_ctrl node
arm64: dts: ti: j7200-main: Fix 'dtbs_check' serdes_ln_ctrl node
arm64: dts: ti: k3-j721e: correct cache-sets info
Link: https://lore.kernel.org/r/20211217172806.10023-2-vigneshr@ti.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Mon, 20 Dec 2021 14:49:16 +0000 (15:49 +0100)]
Merge tag 'tegra-for-5.17-arm64-dt' of git://git./linux/kernel/git/tegra/linux into arm/dt
arm64: tegra: Device tree changes for v5.17-rc1
The vast majority of this contains various updates and cleanups to the
Tegra device trees that will eventually help validate all of them using
the dt-schema infrastructure.
Another notable chunk of this contains additional Tegra234 support as
well as support for the new Jetson AGX Orin Developer Kit.
* tag 'tegra-for-5.17-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: (47 commits)
arm64: tegra: Add host1x hotflush reset on Tegra210
arm64: tegra: Hook up MMC and BPMP to memory controller
arm64: tegra: Add memory controller on Tegra234
arm64: tegra: Add EMC general interrupt on Tegra194
arm64: tegra: Update SDMMC4 speeds for Tegra194
arm64: tegra: Add dma-coherent for Tegra194 VIC
arm64: tegra: Rename Ethernet PHY nodes
arm64: tegra: Remove unused only-1-8-v properties
arm64: tegra: Sort Tegra210 XUSB clocks correctly
arm64: tegra: Add missing TSEC properties on Tegra210
arm64: tegra: jetson-nano: Remove extra PLL power supplies for PCIe and XUSB
arm64: tegra: smaug: Remove extra PLL power supplies for XUSB
arm64: tegra: jetson-tx1: Remove extra PLL power supplies for PCIe and XUSB
arm64: tegra: Rename GPIO hog nodes to match schema
arm64: tegra: Remove unsupported regulator properties
arm64: tegra: Rename TCU node to "serial"
arm64: tegra: Remove undocumented Tegra194 PCIe "core_m" clock
arm64: tegra: Drop unused properties for Tegra194 PCIe
arm64: tegra: Fix Tegra194 HSP compatible string
arm64: tegra: Drop unsupported nvidia,lpdr property
...
Link: https://lore.kernel.org/r/20211217162253.1801077-4-thierry.reding@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Mon, 20 Dec 2021 14:37:23 +0000 (15:37 +0100)]
Merge tag 'tegra-for-5.17-dt-bindings' of git://git./linux/kernel/git/tegra/linux into arm/dt
dt-bindings: Changes for v5.17-rc1
This contains a bunch of json-schema conversions for various Tegra-
related DT bindings and additions for new SoC and board support.
* tag 'tegra-for-5.17-dt-bindings' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: (30 commits)
media: dt: bindings: tegra-vde: Document OPP and power domain
media: dt: bindings: tegra-vde: Convert to schema
dt-bindings: host1x: Document Memory Client resets of Host1x, GR2D and GR3D
dt-bindings: host1x: Document OPP and power domain properties
dt-bindings: clock: tegra-car: Document new clock sub-nodes
dt-bindings: ARM: tegra: Document Pegatron Chagall
dt-bindings: ARM: tegra: Document ASUS Transformers
dt-bindings: usb: tegra-xudc: Document interconnects and iommus properties
dt-bindings: serial: Document Tegra234 TCU
dt-bindings: serial: tegra-tcu: Convert to json-schema
dt-bindings: thermal: tegra186-bpmp: Convert to json-schema
dt-bindings: firmware: tegra: Convert to json-schema
dt-bindings: tegra: pmc: Convert to json-schema
dt-bindings: serial: 8250: Document Tegra234 UART
dt-bindings: mmc: tegra: Document Tegra234 SDHCI
dt-bindings: fuse: tegra: Document Tegra234 FUSE
dt-bindings: fuse: tegra: Convert to json-schema
dt-bindings: rtc: tegra: Document Tegra234 RTC
dt-bindings: rtc: tegra: Convert to json-schema
dt-bindings: mailbox: tegra: Document Tegra234 HSP
...
Link: https://lore.kernel.org/r/20211217162253.1801077-3-thierry.reding@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Fri, 17 Dec 2021 14:54:22 +0000 (15:54 +0100)]
Merge tag 'renesas-dt-bindings-for-v5.17-tag2' of git://git./linux/kernel/git/geert/renesas-devel into arm/dt
Renesas DT binding updates for v5.17 (take two)
- Document support for the R-Car S4-8 Spider CPU and BreakOut boards.
* tag 'renesas-dt-bindings-for-v5.17-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
dt-bindings: arm: renesas: Document Renesas Spider boards
Link: https://lore.kernel.org/r/cover.1639736725.git.geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Fri, 17 Dec 2021 14:53:29 +0000 (15:53 +0100)]
Merge tag 'renesas-arm-dt-for-v5.17-tag2' of git://git./linux/kernel/git/geert/renesas-devel into arm/dt
Renesas ARM DT updates for v5.17 (take two)
- Initial support for the R-Car S4-8 SoC on the Spider CPU and
BreakOut boards,
- MIPI DSI display support for the R-Car V3u SoC and the Falcon board
stack,
- Thermal and GPU support for the RZ/G2L SoC and the RZ/G2L SMARC EVK
development board,
- Miscellaneous fixes and improvements.
* tag 'renesas-arm-dt-for-v5.17-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
arm64: dts: renesas: Fix pin controller node names
arm64: dts: renesas: rzg2l-smarc-som: Add vdd core regulator
arm64: dts: renesas: r9a07g044: Add Mali-G31 GPU node
arm64: dts: renesas: r9a07g044: Create thermal zone to support IPA
arm64: dts: renesas: r9a07g044: Add TSU node
arm64: dts: renesas: falcon-cpu: Add DSI display output
arm64: dts: renesas: r8a779a0: Add DSI encoders
arm64: dts: renesas: Add Renesas Spider boards support
arm64: dts: renesas: Add Renesas R8A779F0 SoC support
dt-bindings: clock: Add r8a779f0 CPG Core Clock Definitions
dt-bindings: power: Add r8a779f0 SYSC power domain definitions
arm64: dts: renesas: Fix thermal bindings
Link: https://lore.kernel.org/r/cover.1639736718.git.geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Fri, 17 Dec 2021 14:52:07 +0000 (15:52 +0100)]
Merge tag 'sunxi-dt-for-5.17-1' of git://git./linux/kernel/git/sunxi/linux into arm/dt
Our usual round of DT patches for the 5.17 merge window, with:
- Introduction of the chassis-type property
- I2C, SPDIF support for the Tanix TX6
- Memory frequency scaling for the A64 and H5
- Hantro G2 support for the H6
- New Board: Tanix TX6 Mini
* tag 'sunxi-dt-for-5.17-1' of git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
arm64: dts: allwinner: h6: Add Hantro G2 node
arm64: dts: allwinner: h6: tanix-tx6: Enable bluetooth
arm64: dts: allwinner: h6: tanix: Add MMC1 node
arm64: dts: allwinner: h6: Add Tanix TX6 mini dts
dt-bindings: arm: sunxi: Add Tanix TX6 mini
arm64: dts: allwinner: h6: tanix-tx6: Split to DT and DTSI
ARM: dts: sun8i: Adjust power key nodes
arm64: dts: allwinner: a64: Update MBUS node
ARM: dts: sunxi: h3/h5: Update MBUS node
dt-bindings: arm: sunxi: Add H5 MBUS compatible
dt-bindings: arm: sunxi: Expand MBUS binding
dt-bindings: clock: sunxi: Export CLK_DRAM for devfreq
dt-bindings: crypto: Add optional dma properties
ARM: dts: sun8i: h3: beelink-x2: Add GPIO CEC node
ARM: dts: sunxi: Add CEC clock to DW-HDMI
arm64: dts: allwinner: a64: Add CEC clock to HDMI
ARM: dts: sun8i: h3: beelink-x2: Sort nodes
arm64: dts: allwinner: h6: tanix-tx6: Add I2C node
arm64: dts: allwinner: h6: tanix-tx6: Add SPDIF
arm64: dts: allwinner: add 'chassis-type' property
Link: https://lore.kernel.org/r/ef385139-6fd4-42d2-9bfe-a4dda7ac76c9.lettre@localhost
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Thierry Reding [Fri, 17 Dec 2021 13:53:08 +0000 (14:53 +0100)]
arm64: tegra: Add host1x hotflush reset on Tegra210
Add the host1x memory client hotflush reset on Tegra210.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Dmitry Osipenko [Tue, 30 Nov 2021 23:23:33 +0000 (02:23 +0300)]
media: dt: bindings: tegra-vde: Document OPP and power domain
Document new OPP table and power domain properties of the video decoder
hardware.
Reviewed-by: Rob Herring <robh@kernel.org>
Acked-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Dmitry Osipenko [Tue, 30 Nov 2021 23:23:32 +0000 (02:23 +0300)]
media: dt: bindings: tegra-vde: Convert to schema
Convert NVIDIA Tegra video decoder binding to schema.
Reviewed-by: Rob Herring <robh@kernel.org>
Acked-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Dmitry Osipenko [Tue, 30 Nov 2021 23:23:14 +0000 (02:23 +0300)]
dt-bindings: host1x: Document Memory Client resets of Host1x, GR2D and GR3D
Memory Client should be blocked before hardware reset is asserted in order
to prevent memory corruption and hanging of memory controller.
Document Memory Client resets of Host1x, GR2D and GR3D hardware units.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Dmitry Osipenko [Tue, 30 Nov 2021 23:23:13 +0000 (02:23 +0300)]
dt-bindings: host1x: Document OPP and power domain properties
Document new DVFS OPP table and power domain properties of the Host1x bus
and devices sitting on the bus.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Dmitry Osipenko [Tue, 30 Nov 2021 23:23:11 +0000 (02:23 +0300)]
dt-bindings: clock: tegra-car: Document new clock sub-nodes
Document sub-nodes which describe Tegra SoC clocks that require a higher
voltage of the core power domain in order to operate properly on a higher
clock rates. Each node contains a phandle to OPP table and power domain.
The root PLLs and system clocks don't have any specific device dedicated
to them, clock controller is in charge of managing power for them.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
David Heidelberg [Sat, 11 Dec 2021 21:13:46 +0000 (00:13 +0300)]
dt-bindings: ARM: tegra: Document Pegatron Chagall
Document Pegatron Chagall, which is Tegra30-based tablet device.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: David Heidelberg <david@ixit.cz>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Svyatoslav Ryhel [Sat, 11 Dec 2021 21:13:45 +0000 (00:13 +0300)]
dt-bindings: ARM: tegra: Document ASUS Transformers
Document Tegra20/30/114-based ASUS Transformer Series tablet devices.
This group includes EeePad TF101, Prime TF201, Pad TF300T, TF300TG
Infinity TF700T, TF701T.
Signed-off-by: David Heidelberg <david@ixit.cz>
Signed-off-by: Anton Bambura <jenneron@protonmail.com>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Thierry Reding [Mon, 6 Dec 2021 15:55:59 +0000 (16:55 +0100)]
dt-bindings: usb: tegra-xudc: Document interconnects and iommus properties
Add the interconnects, interconnect-names and iommus properties to the
device tree bindings for the Tegra XUDC controller. These are used to
describe the device's paths to and from memory.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Thierry Reding [Fri, 19 Nov 2021 14:38:39 +0000 (15:38 +0100)]
dt-bindings: serial: Document Tegra234 TCU
Add the compatible string for the TCU found on the Tegra234 SoC.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Thierry Reding [Fri, 19 Nov 2021 14:38:38 +0000 (15:38 +0100)]
dt-bindings: serial: tegra-tcu: Convert to json-schema
Convert the Tegra TCU device tree bindings to json-schema.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Thierry Reding [Fri, 19 Nov 2021 14:38:37 +0000 (15:38 +0100)]
dt-bindings: thermal: tegra186-bpmp: Convert to json-schema
Convert the Tegra186 (and later) BPMP thermal device tree bindings from
the free-form text format to json-schema.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Thierry Reding [Fri, 19 Nov 2021 14:38:35 +0000 (15:38 +0100)]
dt-bindings: firmware: tegra: Convert to json-schema
Convert the NVIDIA Tegra186 (and later) BPMP bindings from the free-form
text format to json-schema.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Thierry Reding [Fri, 19 Nov 2021 14:38:34 +0000 (15:38 +0100)]
dt-bindings: tegra: pmc: Convert to json-schema
Convert the NVIDIA Tegra186 (and later) PMC bindings from the free-form
text format to json-schema.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Thierry Reding [Fri, 19 Nov 2021 14:38:33 +0000 (15:38 +0100)]
dt-bindings: serial: 8250: Document Tegra234 UART
Add the compatible string for the UART found on the Tegra234 SoC.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Thierry Reding [Fri, 19 Nov 2021 14:38:32 +0000 (15:38 +0100)]
dt-bindings: mmc: tegra: Document Tegra234 SDHCI
Add the compatible string for the SDHCI block found on the Tegra234 SoC.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Thierry Reding [Fri, 19 Nov 2021 14:38:31 +0000 (15:38 +0100)]
dt-bindings: fuse: tegra: Document Tegra234 FUSE
Add the compatible string for the FUSE block found on the Tegra234 SoC.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Thierry Reding [Fri, 19 Nov 2021 14:38:30 +0000 (15:38 +0100)]
dt-bindings: fuse: tegra: Convert to json-schema
Convert the NVIDIA Tegra FUSE bindings from the free-form text format to
json-schema.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Thierry Reding [Fri, 19 Nov 2021 14:38:29 +0000 (15:38 +0100)]
dt-bindings: rtc: tegra: Document Tegra234 RTC
Add the compatible string for the RTC block found on the Tegra234 SoC.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Thierry Reding [Fri, 19 Nov 2021 14:38:28 +0000 (15:38 +0100)]
dt-bindings: rtc: tegra: Convert to json-schema
Convert the NVIDIA Tegra RTC bindings from the free-form text format to
json-schema.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Thierry Reding [Fri, 19 Nov 2021 14:38:27 +0000 (15:38 +0100)]
dt-bindings: mailbox: tegra: Document Tegra234 HSP
Add the compatible string for the HSP block found on the Tegra234 SoC.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Thierry Reding [Fri, 19 Nov 2021 14:38:26 +0000 (15:38 +0100)]
dt-bindings: mailbox: tegra: Convert to json-schema
Convert the NVIDIA Tegra HSP bindings from the free-form text format to
json-schema.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Thierry Reding [Fri, 19 Nov 2021 14:38:25 +0000 (15:38 +0100)]
dt-bindings: mmc: tegra: Convert to json-schema
Convert the NVIDIA Tegra SDHCI bindings from the free-form text format
to json-schema.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Geert Uytterhoeven [Thu, 16 Dec 2021 15:04:49 +0000 (16:04 +0100)]
arm64: dts: renesas: Fix pin controller node names
Align all pin controller node names with the expectations of the DT
bindings in Documentation/devicetree/bindings/pinctrl/pinctrl.yaml.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/09a09c8ac9cb1a11b859c1ab9d9eae84cfefb1bb.1639666967.git.geert+renesas@glider.be
Thierry Reding [Mon, 13 Dec 2021 16:21:51 +0000 (17:21 +0100)]
arm64: tegra: Hook up MMC and BPMP to memory controller
Use the interconnects property to hook up the MMC and BPMP to the memory
controller. This is needed to set the correct bus-level DMA mask, which
is a prerequisite for adding IOMMU support.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Thierry Reding [Mon, 13 Dec 2021 16:21:50 +0000 (17:21 +0100)]
arm64: tegra: Add memory controller on Tegra234
This adds the memory controller and the embedded external memory
controller found on the Tegra234 SoC.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Thierry Reding [Mon, 13 Dec 2021 16:21:49 +0000 (17:21 +0100)]
arm64: tegra: Add EMC general interrupt on Tegra194
Add the missing EMC general interrupt for the external memory controller
on Tegra194.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Prathamesh Shete [Thu, 16 Dec 2021 09:46:10 +0000 (15:16 +0530)]
arm64: tegra: Update SDMMC4 speeds for Tegra194
Add required device-tree properties to populate all speed
modes supported by SDMMC4 instance of Tegra194 SDHCI controller.
Signed-off-by: Prathamesh Shete <pshete@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Jon Hunter [Mon, 25 Oct 2021 11:08:42 +0000 (12:08 +0100)]
arm64: tegra: Add dma-coherent for Tegra194 VIC
DMA operations for the Tegra194 Video Image Compositor (VIC) are
coherent and so populate the 'dma-coherent' property.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Thierry Reding [Wed, 8 Dec 2021 15:29:11 +0000 (16:29 +0100)]
arm64: tegra: Rename Ethernet PHY nodes
Name the Ethernet PHY device tree nodes as expected by the DT schema.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Thierry Reding [Tue, 7 Dec 2021 14:06:19 +0000 (15:06 +0100)]
arm64: tegra: Remove unused only-1-8-v properties
The only-1-8-v property is not support by an DT schema, so drop it.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Thierry Reding [Tue, 7 Dec 2021 14:05:32 +0000 (15:05 +0100)]
arm64: tegra: Sort Tegra210 XUSB clocks correctly
Make the order of the clocks and clock-names properties match the order
in the device tree bindings. This isn't strictly necessary from a point
of view of the operating system because matching will be done based on
the clock-names, but it makes it easier to validate the device trees
against the DT schema.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Thierry Reding [Tue, 7 Dec 2021 14:01:37 +0000 (15:01 +0100)]
arm64: tegra: Add missing TSEC properties on Tegra210
Add missing interrupts, clocks, clock-names, reset and reset-names
properties for the TSEC blocks found on Tegra210.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Thierry Reding [Fri, 22 Mar 2019 13:56:11 +0000 (14:56 +0100)]
arm64: tegra: jetson-nano: Remove extra PLL power supplies for PCIe and XUSB
The XUSB pad controller handles the various PLL power supplies, so
remove any references to them from the PCIe and XUSB controller device
tree nodes.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Thierry Reding [Fri, 22 Mar 2019 13:43:03 +0000 (14:43 +0100)]
arm64: tegra: smaug: Remove extra PLL power supplies for XUSB
The XUSB pad controller handles the various PLL power supplies, so
remove any references to them from the XUSB controller device tree
node.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Thierry Reding [Fri, 22 Mar 2019 13:41:53 +0000 (14:41 +0100)]
arm64: tegra: jetson-tx1: Remove extra PLL power supplies for PCIe and XUSB
The XUSB pad controller handles the various PLL power supplies, so
remove any references to them from the PCIe and XUSB controller device
tree nodes.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Thierry Reding [Tue, 7 Dec 2021 13:54:48 +0000 (14:54 +0100)]
arm64: tegra: Rename GPIO hog nodes to match schema
GPIO hog nodes must have a "hog-" prefix or "-hog" suffix according to
the DT schema. Rename all such nodes to allow validation to pass.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Thierry Reding [Tue, 7 Dec 2021 13:53:28 +0000 (14:53 +0100)]
arm64: tegra: Remove unsupported regulator properties
Remove the unsupported "regulator-disable-ramp-delay" properties which
ended up in various DTS files for some reason.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Thierry Reding [Tue, 7 Dec 2021 13:51:54 +0000 (14:51 +0100)]
arm64: tegra: Rename TCU node to "serial"
The TCU is basically a serial port (albeit a fancy one), so it should be
named "serial".
Signed-off-by: Thierry Reding <treding@nvidia.com>
Thierry Reding [Tue, 7 Dec 2021 13:50:44 +0000 (14:50 +0100)]
arm64: tegra: Remove undocumented Tegra194 PCIe "core_m" clock
The "core_m" clock is not documented in the Tegra194 PCIe device tree
bindings, so remove it.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Thierry Reding [Tue, 7 Dec 2021 13:47:47 +0000 (14:47 +0100)]
arm64: tegra: Drop unused properties for Tegra194 PCIe
The num-viewport property is never used and can be dropped, whereas the
"iommus" property is not needed since we use "iommu-map-mask" and
"iommu-map" already.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Thierry Reding [Tue, 7 Dec 2021 13:43:20 +0000 (14:43 +0100)]
arm64: tegra: Fix Tegra194 HSP compatible string
The HSP instances on Tegra194 are not fully compatible with the version
found on Tegra186, so drop the fallback compatible string from the list.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Thierry Reding [Tue, 7 Dec 2021 13:40:59 +0000 (14:40 +0100)]
arm64: tegra: Drop unsupported nvidia,lpdr property
The Tegra194 pinmux DT bindings do not define the nvidia,lpdr property,
so drop them from the device trees that have listed them.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Thierry Reding [Tue, 7 Dec 2021 13:39:20 +0000 (14:39 +0100)]
arm64: tegra: Use JEDEC vendor prefix for SPI NOR flash chips
The standard "jedec," vendor prefix should be used for SPI NOR flash
chips. This allows the right DT schema to be picked for validation.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Thierry Reding [Tue, 7 Dec 2021 13:36:35 +0000 (14:36 +0100)]
arm64: tegra: Drop unit-address for audio card graph endpoints
Audio graph endpoints don't have a "reg" property, so they shouldn't
have a unit-address either.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Thierry Reding [Tue, 7 Dec 2021 13:28:29 +0000 (14:28 +0100)]
arm64: tegra: Adjust length of CCPLEX cluster MMIO region
The Tegra186 CCPLEX cluster register region is 4 MiB is length, not 4
MiB - 1. This was likely presumed to be the "limit" rather than length.
Fix it up.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Thierry Reding [Tue, 7 Dec 2021 13:27:11 +0000 (14:27 +0100)]
arm64: tegra: Fix Tegra186 compatible string list
The I2C controller found on Tegra186 is not fully compatible with the
Tegra210 version, so drop the fallback compatible string from the list.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Thierry Reding [Tue, 7 Dec 2021 13:25:50 +0000 (14:25 +0100)]
arm64: tegra: Rename power-monitor input nodes
Child nodes of the TI INA3221 power monitor device tree node should be
called input@* according to the DT schema.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Thierry Reding [Tue, 7 Dec 2021 13:24:20 +0000 (14:24 +0100)]
arm64: tegra: Rename thermal zones nodes
The DT schema requires that nodes representing thermal zones include a
"-thermal" suffix in their name.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Thierry Reding [Tue, 7 Dec 2021 13:21:18 +0000 (14:21 +0100)]
arm64: tegra: Sort Tegra132 XUSB clocks correctly
Make the order of the clocks and clock-names properties match the order
in the device tree bindings. This isn't strictly necessary from a point
of view of the operating system because matching will be done based on
the clock-names, but it makes it easier to validate the device trees
against the DT schema.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Thierry Reding [Tue, 7 Dec 2021 13:20:25 +0000 (14:20 +0100)]
arm64: tegra: Drop unused AHCI clocks on Tegra132
The CML1 and PLL_E clocks are never explicitly used by the AHCI
controller found on Tegra132, so drop them from the corresponding device
tree node.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Thierry Reding [Tue, 7 Dec 2021 13:19:26 +0000 (14:19 +0100)]
arm64: tegra: Fix Tegra132 I2C compatible string list
The I2C controller found on Tegra124 is not fully compatible with the
Tegra114 version, so drop the fallback compatible string from the list.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Thierry Reding [Tue, 7 Dec 2021 13:17:07 +0000 (14:17 +0100)]
arm64: tegra: Add OPP tables on Tegra132
Add peripheral OPP tables on Tegra132 and wire them up to ACTMON and the
EMC. While at it, add the missing "#interconnect-cells" properties to
the memory controller and external memory controller nodes. Also set the
"#reset-cells" property for the memory controller because it exports the
hotflush reset controls.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Thierry Reding [Tue, 7 Dec 2021 13:13:37 +0000 (14:13 +0100)]
arm64: tegra: Fix compatible string for Tegra132 timer
The TKE (time-keeping engine) found on Tegra132 is not backwards
compatible with the version found on Tegra20, so update the compatible
string list accordingly.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Thierry Reding [Tue, 7 Dec 2021 13:11:53 +0000 (14:11 +0100)]
arm64: tegra: Remove unsupported properties on Norrin
The Tegra PMC device tree bindings don't support the "#wake-cells" and
"nvidia,reset-gpio" properties, so remove them.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Thierry Reding [Tue, 7 Dec 2021 13:10:00 +0000 (14:10 +0100)]
arm64: tegra: Fix unit-addresses on Norrin
The AS3722 pinmux device tree node doesn't have a "reg" property and
therefore must not have a unit-address, so drop it.
While at it, add missing unit-addresses for the charger and smart
battery IC's on the ChromeOS embedded controller's I2C tunnel bus.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Thierry Reding [Thu, 19 Mar 2020 15:45:38 +0000 (16:45 +0100)]
arm64: tegra: Add native timer support on Tegra186
The native timers IP block found on NVIDIA Tegra SoCs implements a
watchdog timer that can be used to recover from system hangs. Add the
device tree node on Tegra186.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Thierry Reding [Mon, 6 Dec 2021 17:02:18 +0000 (18:02 +0100)]
arm64: tegra: Rename top-level regulators
Regulators defined at the top level in device tree are no longer part of
a simple bus and therefore don't have a reg property. Nodes without a
reg property shouldn't have a unit-address either, so drop the unit
address from the node names. To ensure nodes aren't duplicated (in which
case they would end up merged in the final DTB), append the name of the
regulator to the node name.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Thierry Reding [Mon, 6 Dec 2021 16:58:55 +0000 (17:58 +0100)]
arm64: tegra: Rename top-level clocks
Clocks defined at the top level in device tree are no longer part of a
simple bus and therefore don't have a reg property. Nodes without a reg
property shouldn't have a unit-address either, so drop the unit address
from the node names. To ensure nodes aren't duplicated (in which case
they would end up merged in the final DTB), append the name of the clock
to the node name.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Jon Hunter [Wed, 1 Dec 2021 15:57:16 +0000 (15:57 +0000)]
arm64: tegra: Add ISO SMMU controller for Tegra194
The display controllers are attached to a separate ARM SMMU instance
that is dedicated to servicing isochronous memory clients. Add this ISO
instance of the ARM SMMU to device tree.
Please note that the display controllers are not hooked up to this SMMU
yet, because we are still missing a means to transition framebuffers
used by the bootloader to the kernel.
This based upon an initial patch by Thierry Reding <treding@nvidia.com>.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Jon Hunter [Wed, 17 Nov 2021 09:56:08 +0000 (09:56 +0000)]
arm64: tegra: Add NVENC and NVJPG nodes for Tegra186 and Tegra194
Populate the device-tree nodes for NVENC and NVJPG Host1x engines on
Tegra186 and Tegra194.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Prathamesh Shete [Tue, 16 Nov 2021 12:02:36 +0000 (17:32 +0530)]
arm64: tegra: Add support to enumerate SD in UHS mode
Add support to enumerate SD in UHS mode on Tegra194. Add required
device-tree properties in SDMMC1 and SDMMC3 instances to enable dynamic
pad voltage switching and enumerate SD card in UHS-I modes.
Signed-off-by: Prathamesh Shete <pshete@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Mikko Perttunen [Fri, 12 Nov 2021 12:35:42 +0000 (13:35 +0100)]
arm64: tegra: Add NVIDIA Jetson AGX Orin Developer Kit support
The Jetson AGX Orin Developer Kit is a continuation of the Jetson
Developer Kit line using the new NVIDIA Tegra234 (Orin) SoC.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Thierry Reding [Fri, 12 Nov 2021 13:19:04 +0000 (14:19 +0100)]
arm64: tegra: Describe Tegra234 CPU hierarchy
The NVIDIA Tegra234 SoC has 3 clusters of 4 Cortex-A78AE CPU cores each,
for a total of 12 CPUs. Each CPU has 64 KiB instruction and data caches
with each cluster having an additional 256 KiB unified L2 cache and a 2
MiB L3 cache.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Thierry Reding [Fri, 10 Dec 2021 16:02:05 +0000 (17:02 +0100)]
arm64: tegra: Add main and AON GPIO controllers on Tegra234
These two controllers expose general purpose I/O pins that can be used
to control or monitor a variety of signals.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Mikko Perttunen [Fri, 12 Nov 2021 12:35:41 +0000 (13:35 +0100)]
arm64: tegra: Add Tegra234 TCU device
Add a device for TCU (Tegra Combined UART) used for serial console.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Mikko Perttunen [Fri, 12 Nov 2021 12:35:40 +0000 (13:35 +0100)]
arm64: tegra: Fill in properties for Tegra234 eMMC
Add missing properties to the eMMC controller, as required to use it on
actual hardware.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Mikko Perttunen [Fri, 12 Nov 2021 12:35:39 +0000 (13:35 +0100)]
arm64: tegra: Update Tegra234 BPMP channel addresses
On final Tegra234 systems, shared memory for communication with BPMP is
located at offset 0x70000 in SYSRAM.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Mikko Perttunen [Fri, 12 Nov 2021 12:35:38 +0000 (13:35 +0100)]
arm64: tegra: Add clock for Tegra234 RTC
The RTC device requires a clock. Add it.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Thierry Reding [Fri, 12 Nov 2021 12:35:37 +0000 (13:35 +0100)]
arm64: tegra: Fixup SYSRAM references
The json-schema bindings for SRAM expect the nodes to be called "sram"
rather than "sysram" or "shmem". Furthermore, place the brackets around
the SYSRAM references such that a two-element array is created rather
than a two-element array nested in a single-element array. This is not
relevant for device tree itself, but allows the nodes to be properly
validated against json-schema bindings.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Thierry Reding [Thu, 16 Dec 2021 15:50:49 +0000 (16:50 +0100)]
Merge tag 'tegra-for-5.17-dt-bindings-memory' into for-5.17/arm64/dt
dt-bindings: memory: Add Tegra234 support
This stable tag contains the addition of the EMC clock ID and an initial
list of memory client IDs for Tegra234 and will be shared between the
memory and ARM SoC trees.
Thierry Reding [Fri, 19 Nov 2021 14:38:24 +0000 (15:38 +0100)]
dt-bindings: misc: Convert Tegra MISC to json-schema
Convert the device tree bindings for the MISC register block found on
NVIDIA Tegra SoCs from plain text to json-schema format.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Thierry Reding [Mon, 13 Dec 2021 16:21:47 +0000 (17:21 +0100)]
dt-bindings: memory: tegra: Add Tegra234 support
Document the variant of the memory controller and external memory
controllers found on Tegra234 and add some memory client and SMMU
stream ID definitions for use in device tree files.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Jon Hunter [Wed, 17 Nov 2021 09:56:07 +0000 (09:56 +0000)]
dt-bindings: Add YAML bindings for NVENC and NVJPG
Add YAML device tree bindings for the Tegra NVENC and NVJPG Host1x
engines.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Thierry Reding [Mon, 13 Dec 2021 16:21:46 +0000 (17:21 +0100)]
dt-bindings: memory: tegra: Update for Tegra194
The #interconnect-cells properties are required to hook up memory
clients to the MC/EMC in interconnects properties. Add a description for
these properties.
For the nested EMC controller, the list of required properties was
missing. Add it so that the validation can be more strict.
Also, allow multiple reg entries required by Tegra194 and later.
While at it, also remove the dummy BPMP node from the example because it
is incomplete and fails validation. It's also not necessary for this
file and the BPMP DT schema already has a full example.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Thierry Reding [Fri, 12 Nov 2021 12:35:35 +0000 (13:35 +0100)]
dt-bindings: sram: Document NVIDIA Tegra SYSRAM
Tegra SoCs have extra on-chip RAM that can be used for inter-processor
communication. Tegra186 and later make use of it to establish a two-way
channel between the CCPLEX and BPMP. Add missing compatible strings for
Tegra186 and Tegra194 as well as a new compatible string for Tegra234.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Mikko Perttunen [Fri, 12 Nov 2021 12:35:34 +0000 (13:35 +0100)]
dt-bindings: Update headers for Tegra234
Add a few more clocks that will be used in follow-up patches to enable
more functionality on Tegra234.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Thierry Reding [Fri, 12 Nov 2021 12:35:33 +0000 (13:35 +0100)]
dt-bindings: tegra: Document Jetson AGX Orin (and devkit)
Add the compatible strings for the Jetson AGX Orin and the
corresponding developer kit.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Thierry Reding [Fri, 12 Nov 2021 12:35:32 +0000 (13:35 +0100)]
dt-bindings: tegra: Describe recent developer kits consistently
Add descriptions to entries that were missing one and don't try to
combine multiple entries into one to avoid confusion.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Biju Das [Wed, 8 Dec 2021 10:40:26 +0000 (10:40 +0000)]
arm64: dts: renesas: rzg2l-smarc-som: Add vdd core regulator
Add vdd core regulator (1.1 V).
This patch add regulator support for gpu.
The H/W manual mentions nothing about a gpu regulator. So using vdd
core regulator for gpu.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20211208104026.421-4-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Biju Das [Wed, 8 Dec 2021 10:40:25 +0000 (10:40 +0000)]
arm64: dts: renesas: r9a07g044: Add Mali-G31 GPU node
Add Mali-G31 GPU node to SoC DTSI.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20211208104026.421-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Arnd Bergmann [Thu, 16 Dec 2021 14:00:32 +0000 (15:00 +0100)]
Merge tag 'omap-for-v5.17/dt-signed' of git://git./linux/kernel/git/tmlind/linux-omap into arm/dt
Devicetree changes for omaps for v5.17 merge window
These changes are mostly minor non-urgent fixes for typos and binding checks.
The system-power-controller gets configured for more am3 devices as it's not
am335x-boneblack speicif. For for am437x we add magnetic card reader support.
Note that the asahi-kasei,ak8975 binding changes may produce a new binding
check warning as the binding related change is merged separately.
* tag 'omap-for-v5.17/dt-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: dts: am335x: Use correct vendor prefix for Asahi Kasei Corp.
ARM: dts: motorola-mapphone: Drop second ti,wlcore compatible value
ARM: dts: am437x-gp-evm: enable ADC1
ARM: dts: am43xx: Describe the magnetic reader/ADC1 hardware module
ARM: dts: am437x-cm-t43: Use a correctly spelled DT property
ARM: dts: am335x-icev2: Add system-power-controller to RTC node
ARM: dts: am335x-boneblack-common: move system-power-controller
ARM: dts: elpida_ecb240abacn: Change Elpida compatible
Link: https://lore.kernel.org/r/pull-1639659798-679261@atomide.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Thu, 16 Dec 2021 13:51:42 +0000 (14:51 +0100)]
Merge tag 'socfpga_dts_update_for_v5.17' of git://git./linux/kernel/git/dinguyen/linux into arm/dt
SoCFPGA dts updates for v5.17
- Update N5X to include qspi, usb and ethernet
- Adjust NAND partition size for Agilex and Stratix10
* tag 'socfpga_dts_update_for_v5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux:
arm64: dts: Update NAND MTD partition for Agilex and Stratix 10
arm64: dts: n5x: add qspi, usb, and ethernet support
Link: https://lore.kernel.org/r/20211215164545.300273-1-dinguyen@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Jernej Skrabec [Mon, 29 Nov 2021 18:26:33 +0000 (19:26 +0100)]
arm64: dts: allwinner: h6: Add Hantro G2 node
H6 SoC has a second VPU, dedicated to VP9 decoding. It's a slightly
older design, though.
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20211129182633.480021-10-jernej.skrabec@gmail.com
Arnd Bergmann [Wed, 15 Dec 2021 14:56:39 +0000 (15:56 +0100)]
Merge tag 'asahi-soc-dt-5.17-v2' of https://github.com/AsahiLinux/linux into arm/dt
Apple SoC DT updates for 5.17, round 2:
- Various cleanups (removing useless props, sorting nodes, renaming
things)
- Add PMGR min-state binding & props (see PMGR pull for driver change)
- Initial compatibles for t600x machines (M1 Pro/Max). This covers the
bindings that just need compatible bumps & minor tweaks, no driver
changes.
- Add watchdog node (driver not merged yet, hopefully will be; binding
went in the previous pull)
- Add missing power-domains property to the mailbox binding
* tag 'asahi-soc-dt-5.17-v2' of https://github.com/AsahiLinux/linux:
dt-bindings: mailbox: apple,mailbox: Add power-domains property
arm64: dts: apple: t8103: Sort nodes by address
arm64: dts: apple: t8103: Rename clk24 to clkref
arm64: dts: apple: t8103: Add watchdog node
dt-bindings: pinctrl: apple,pinctrl: Add apple,t6000-pinctrl compatible
dt-bindings: pci: apple,pcie: Add t6000 support
dt-bindings: i2c: apple,i2c: Add apple,t6000-i2c compatible
dt-bindings: arm: apple: Add t6000/t6001 MacBook Pro 14/16" compatibles
arm64: dts: apple: t8103: Add apple,min-state to DCP PMGR nodes
dt-bindings: power: apple,pmgr-pwrstate: Add apple,min-state prop
arm64: dts: apple: t8103: Remove PCIe max-link-speed properties
Link: https://lore.kernel.org/r/a24faafd-f2ae-c3a7-5327-b27da7d9e34b@marcan.st
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Wed, 15 Dec 2021 14:55:30 +0000 (15:55 +0100)]
Merge tag 'stm32-dt-for-v5.17-1' of git://git./linux/kernel/git/atorgue/stm32 into arm/dt
STM32 DT for v5.17, round 1
Highlights:
----------
-MCU:
- fix ili9341 for dtbs_check warnings on stm32f429 disco.
- MPU:
- ST boards:
- tune HS USB phys on stm32mp15 EV1 and DKx boards.
- add pull-up on USART3/UART7 RX pins on STM32MP15 DKx boards.
- use correct pinctrl setting for STUSB1600 on STM32MP15 DK boards.
- ENGICAM:
- enable LVDS pannel on i.Core STM32MP1 EDIMM2.2.
- add "i.Core STM32MP1 C.TOUCH 2.0 10.1" OF" support:
EDIMM compliant general purpose carrier board with ETH 10/100,
WIFI/BT, CAN, ...
* tag 'stm32-dt-for-v5.17-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32:
ARM: dts: stm32: Add Engicam i.Core STM32MP1 C.TOUCH 2.0 10.1" OF
dt-bindings: arm: stm32: Add Engicam i.Core STM32MP1 C.TOUCH 2.0 10.1" OF
ARM: dts: stm32: Enable LVDS panel on i.Core STM32MP1 EDIMM2.2
ARM: dts: stm32: fix stusb1600 pinctrl used on stm32mp157c-dk
ARM: dts: stm32: tune the HS USB PHYs on stm32mp157c-ev1
ARM: dts: stm32: tune the HS USB PHYs on stm32mp15xx-dkx
ARM: dts: stm32: clean uart4_idle_pins_a node for stm32mp15
ARM: dts: stm32: add pull-up to USART3 and UART7 RX pins on STM32MP15 DKx boards
ARM: dts: stm32: fix dtbs_check warning on ili9341 dts binding on stm32f429 disco
Link: https://lore.kernel.org/r/dfe942db-5af7-bb82-22b6-3bd866c9017d@foss.st.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Hector Martin [Thu, 9 Dec 2021 04:50:42 +0000 (13:50 +0900)]
dt-bindings: mailbox: apple,mailbox: Add power-domains property
This will bind to the PMGR pwrstate nodes that control power/clock
gating to SoC blocks. The mailbox driver doesn't do runtime-pm yet, so
initially this will just keep the domain on permanently.
Reviewed-by: Sven Peter <sven@svenpeter.dev>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Hector Martin <marcan@marcan.st>
Hector Martin [Sun, 12 Dec 2021 01:40:16 +0000 (10:40 +0900)]
arm64: dts: apple: t8103: Sort nodes by address
We decided to keep SoC nodes sorted by address for sanity; fix a couple
that slipped into the wrong place.
Reviewed-by: Sven Peter <sven@svenpeter.dev>
Signed-off-by: Hector Martin <marcan@marcan.st>
Hector Martin [Tue, 5 Oct 2021 14:24:21 +0000 (23:24 +0900)]
arm64: dts: apple: t8103: Rename clk24 to clkref
We now know that this frequency comes from the external reference
oscillator and is used for various SoC blocks, and isn't just a random
24MHz clock, so let's call it something more appropriate.
Reviewed-by: Mark Kettenis <kettenis@openbsd.org>
Reviewed-by: Sven Peter <sven@svenpeter.dev>
Signed-off-by: Hector Martin <marcan@marcan.st>
Biju Das [Wed, 8 Dec 2021 14:27:29 +0000 (14:27 +0000)]
arm64: dts: renesas: r9a07g044: Create thermal zone to support IPA
Setup a thermal zone driven by SoC temperature sensor.
Create passive trip points and bind them to CPUFreq cooling
device that supports power extension.
Based on the work done by Dien Pham <dien.pham.ry@renesas.com>
and others for r8a77990 SoC.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20211208142729.2456-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Biju Das [Wed, 8 Dec 2021 14:27:28 +0000 (14:27 +0000)]
arm64: dts: renesas: r9a07g044: Add TSU node
Add TSU node to RZ/G2L SoC DTSI.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20211208142729.2456-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Kieran Bingham [Tue, 30 Nov 2021 16:43:11 +0000 (16:43 +0000)]
arm64: dts: renesas: falcon-cpu: Add DSI display output
Provide the display output using the sn65dsi86 MIPI DSI bridge.
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
Link: https://lore.kernel.org/r/20211130164311.2909616-3-kieran.bingham+renesas@ideasonboard.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Kieran Bingham [Tue, 30 Nov 2021 16:43:10 +0000 (16:43 +0000)]
arm64: dts: renesas: r8a779a0: Add DSI encoders
Provide the two MIPI DSI encoders on the V3U and connect them to the DU
accordingly.
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
Link: https://lore.kernel.org/r/20211130164311.2909616-2-kieran.bingham+renesas@ideasonboard.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Arnd Bergmann [Tue, 14 Dec 2021 07:50:16 +0000 (08:50 +0100)]
Merge tag 'ixp4xx-dtx-v5.17' of git://git./linux/kernel/git/linusw/linux-nomadik into arm/dt
IXP4xx DTS changes for v5.17:
- Add the LEDs to the Freecom FSG-3 that were missing.
- Add a devicetree for the Gorami MultiLink Router
- Add a devicetree for the Gateway GW7001 Router
This completes the migration of all IXP4xx devices to
device tree files.
Next merge window we will delete the remaining board files,
it cannot be done now because of cross-tree dependencies.
* tag 'ixp4xx-dtx-v5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik:
ARM: dts: ixp4xx: Add devicetree for Gateway 7001
ARM: dts: Add Goramo MultiLink device tree
ARM: dts: Add FSG3 system controller and LEDs
Link: https://lore.kernel.org/r/CACRpkdYiWK7TEbZrh4_0WT5obMk=ZSc7AQVUSPXL+-uZ_hsUEA@mail.gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
projects / linux.git / log