linux.git
6 years agoMerge branches 'clk-davinci-psc-da830', 'clk-renesas', 'clk-at91-recalc', 'clk-davinc...
Stephen Boyd [Mon, 4 Jun 2018 19:37:41 +0000 (12:37 -0700)]
Merge branches 'clk-davinci-psc-da830', 'clk-renesas', 'clk-at91-recalc', 'clk-davinci' and 'clk-meson' into clk-next

* clk-davinci-psc-da830:
  clk: davinci: psc-da830: fix USB0 48MHz PHY clock registration

* clk-renesas:
  clk: renesas: cpg-mssr: Add support for R-Car E3
  clk: renesas: Add r8a77990 CPG Core Clock Definitions
  clk: renesas: rcar-gen2: Centralize quirks handling
  clk: renesas: r8a77980: Correct parent clock of PCIEC0
  clk: renesas: r8a7794: Fix LB clock divider
  clk: renesas: r8a7792: Fix LB clock divider
  clk: renesas: r8a7791/r8a7793: Fix LB clock divider
  clk: renesas: r8a7745: Fix LB clock divider
  clk: renesas: r8a7743: Fix LB clock divider
  clk: renesas: cpg-mssr: Add r8a77470 support
  clk: renesas: Add r8a77470 CPG Core Clock Definitions
  clk: renesas: r8a77965: Add MSIOF controller clocks

* clk-at91-recalc:
  clk: at91: PLL recalc_rate() now using cached MUL and DIV values

* clk-davinci:
  clk: davinci: Fix link errors when not all SoCs are enabled
  clk: davinci: psc: allow for dev == NULL
  clk: davinci: da850-pll: change PLL0 to CLK_OF_DECLARE
  clk: davinci: pll: allow dev == NULL
  clk: davinci: psc-dm365: fix few clocks
  clk: davinci: pll-dm646x: keep PLL2 SYSCLK1 always enabled
  clk: davinci: psc-dm355: fix ASP0/1 clkdev lookups
  clk: davinci: pll-dm355: fix SYSCLKn parent names
  clk: davinci: pll-dm355: drop pll2_sysclk2

* clk-meson:
  clk: meson: axg: let mpll clocks round closest
  clk: meson: mpll: add round closest support
  clk: meson: meson8b: mark fclk_div2 gate clocks as CLK_IS_CRITICAL
  clk: meson: use SPDX license identifiers consistently
  clk: meson: drop CLK_SET_RATE_PARENT flag
  clk: meson-axg: Add AO Clock and Reset controller driver
  clk: meson: aoclk: refactor common code into dedicated file
  clk: meson: migrate to devm_of_clk_add_hw_provider API
  clk: meson: gxbb: add the video decoder clocks
  clk: meson: meson8b: add support for the NAND clocks
  dt-bindings: clock: reset: Add AXG AO Clock and Reset Bindings
  dt-bindings: clock: axg-aoclkc: New binding for Meson-AXG SoC
  clk: meson: gxbb: expose VDEC_1 and VDEC_HEVC clocks
  dt-bindings: clock: meson8b: export the NAND clock

6 years agoMerge branch 'clk-qcom-8996-halt' into clk-next
Stephen Boyd [Mon, 4 Jun 2018 19:35:59 +0000 (12:35 -0700)]
Merge branch 'clk-qcom-8996-halt' into clk-next

* clk-qcom-8996-halt:
  clk: qcom: gcc-msm8996: Disable halt check on UFS clocks
  clk: msm8996-gcc: Mark halt check as no-op for USB/PCIE pipe_clk

6 years agoMerge branch 'clk-qcom-sdm845' into clk-next
Stephen Boyd [Mon, 4 Jun 2018 19:34:51 +0000 (12:34 -0700)]
Merge branch 'clk-qcom-sdm845' into clk-next

* clk-qcom-sdm845:
  clk: qcom: Export clk_fabia_pll_configure()
  clk: qcom: Add video clock controller driver for SDM845
  dt-bindings: clock: Introduce QCOM Video clock bindings
  clk: qcom: Add Global Clock controller (GCC) driver for SDM845
  clk: qcom: Add DT bindings for SDM845 gcc clock controller
  clk: qcom: Configure the RCGs to a safe source as needed
  clk: qcom: Add support for BRANCH_HALT_SKIP flag for branch clocks
  clk: qcom: Simplify gdsc status checking logic
  clk: qcom: gdsc: Add support to poll CFG register to check GDSC state
  clk: qcom: gdsc: Add support to poll for higher timeout value
  clk: qcom: gdsc: Add support to reset AON and block reset logic
  clk: qcom: Add support for controlling Fabia PLL
  clk: qcom: Clear hardware clock control bit of RCG

Also fixup the Kconfig mess where SDM845 GCC has msm8998 in the
description and also the video Kconfig says things slightly differently
from the GCC one so just make it the same.

6 years agoMerge branches 'clk-match-string', 'clk-ingenic', 'clk-si544-round-fix' and 'clk...
Stephen Boyd [Mon, 4 Jun 2018 19:32:33 +0000 (12:32 -0700)]
Merge branches 'clk-match-string', 'clk-ingenic', 'clk-si544-round-fix' and 'clk-bcm-stingray' into clk-next

* clk-match-string:
  clk: use match_string() helper
  clk: bcm2835: use match_string() helper

* clk-ingenic:
  clk: ingenic: jz4770: Add 150us delay after enabling VPU clock
  clk: ingenic: jz4770: Enable power of AHB1 bus after ungating VPU clock
  clk: ingenic: jz4770: Modify C1CLK clock to disable CPU clock stop on idle
  clk: ingenic: jz4770: Change OTG from custom to standard gated clock
  clk: ingenic: Support specifying "wait for clock stable" delay
  clk: ingenic: Add support for clocks whose gate bit is inverted

* clk-si544-round-fix:
  clk-si544: Properly round requested frequency to nearest match

* clk-bcm-stingray:
  clk: bcm: Update and add Stingray clock entries
  dt-bindings: clk: Update Stingray binding doc

6 years agoMerge branches 'clk-imx7d', 'clk-hisi-stub', 'clk-mvebu', 'clk-imx6-epit' and 'clk...
Stephen Boyd [Mon, 4 Jun 2018 19:32:28 +0000 (12:32 -0700)]
Merge branches 'clk-imx7d', 'clk-hisi-stub', 'clk-mvebu', 'clk-imx6-epit' and 'clk-debugfs-simple' into clk-next

* clk-imx7d:
  clk: imx7d: reset parent for mipi csi root
  clk: imx7d: fix mipi dphy div parent

* clk-hisi-stub:
  clk/driver/hisi: Consolidate the Kconfig for the CLOCK_STUB

* clk-mvebu:
  clk: mvebu: use correct bit for 98DX3236 NAND

* clk-imx6-epit:
  clk: imx6: add EPIT clock support

* clk-debugfs-simple:
  clk: Return void from debug_init op
  clk: remove clk_debugfs_add_file()
  clk: tegra: no need to check return value of debugfs_create functions
  clk: davinci: no need to check return value of debugfs_create functions
  clk: bcm2835: no need to check return value of debugfs_create functions
  clk: no need to check return value of debugfs_create functions

6 years agoMerge branches 'clk-imx6sx', 'clk-imx7d-enet' and 'clk-aspeed-24' into clk-next
Stephen Boyd [Mon, 4 Jun 2018 19:32:24 +0000 (12:32 -0700)]
Merge branches 'clk-imx6sx', 'clk-imx7d-enet' and 'clk-aspeed-24' into clk-next

* clk-imx6sx:
  clk: imx6sl: correct ocram_podf clock type
  clk: imx6sx: disable unnecessary clocks during clock initialization
  clk: imx6sx: add missing lvds2 clock to the clock tree

* clk-imx7d-enet:
  ARM: dts: imx7: correct enet ipg clock
  clk: imx7d: correct enet clock CCGR registers
  clk: imx7d: correct enet phy ref clock gates

* clk-aspeed-24:
  clk: aspeed: Add 24MHz fixed clock

6 years agoMerge branches 'clk-allwinner', 'clk-rockchip', 'clk-tegra', 'clk-berlin' and 'clk...
Stephen Boyd [Mon, 4 Jun 2018 19:27:44 +0000 (12:27 -0700)]
Merge branches 'clk-allwinner', 'clk-rockchip', 'clk-tegra', 'clk-berlin' and 'clk-qcom-mmagic' into clk-next

* clk-allwinner:
  clk: sunxi-ng: r40: export a regmap to access the GMAC register
  clk: sunxi-ng: r40: rewrite init code to a platform driver
  clk: sunxi-ng: add support for H6 PRCM CCU

* clk-rockchip:
  clk: rockchip: remove deprecated gate-clk code and dt-binding
  clk: rockchip: use match_string() helper

* clk-tegra:
  clk: tegra: Add quirk for getting CDEV1/2 clocks on Tegra20
  clk: tegra20: Correct parents of CDEV1/2 clocks
  clk: tegra20: Add DEV1/DEV2 OSC dividers

* clk-berlin:
  clk: berlin: switch to SPDX license identifier

* clk-qcom-mmagic:
  clk: qcom: mmcc-msm8996: leave all mmagic gdscs and clocks always enabled
  clk: qcom: Register the gdscs before the clocks
  clk: qcom: gdsc: Add support for ALWAYS_ON gdscs

6 years agoMerge branches 'clk-hisi-usb', 'clk-silent-bulk', 'clk-mtk-hdmi', 'clk-mtk-mali'...
Stephen Boyd [Mon, 4 Jun 2018 19:27:40 +0000 (12:27 -0700)]
Merge branches 'clk-hisi-usb', 'clk-silent-bulk', 'clk-mtk-hdmi', 'clk-mtk-mali' and 'clk-imx6ul-ccosr' into clk-next

* clk-hisi-usb:
  clk: hisilicon: add missing usb3 clocks for Hi3798CV200 SoC

* clk-silent-bulk:
  clk: bulk: silently error out on EPROBE_DEFER

* clk-mtk-hdmi:
  clk: mediatek: correct the clocks for MT2701 HDMI PHY module

* clk-mtk-mali:
  clk: mediatek: add g3dsys support for MT2701 and MT7623
  dt-bindings: reset: mediatek: add entry for Mali-450 node to refer
  dt-bindings: clock: mediatek: add entry for Mali-450 node to refer
  dt-bindings: clock: mediatek: add g3dsys bindings

* clk-imx6ul-ccosr:
  clk: imx: Add new clo01 and clo2 controlled by CCOSR

6 years agoMerge branches 'clk-stm32mp1', 'clk-samsung', 'clk-uniphier-mpeg', 'clk-stratix10...
Stephen Boyd [Mon, 4 Jun 2018 19:27:34 +0000 (12:27 -0700)]
Merge branches 'clk-stm32mp1', 'clk-samsung', 'clk-uniphier-mpeg', 'clk-stratix10' and 'clk-aspeed' into clk-next

* clk-stm32mp1:
  clk: stm32mp1: Fix a memory leak in 'clk_stm32_register_gate_ops()'
  clk: stm32mp1: Add CLK_IGNORE_UNUSED to ck_sys_dbg clock
  clk: stm32mp1: remove ck_apb_dbg clock
  clk: stm32mp1: set stgen_k clock as critical
  clk: stm32mp1: add missing tzc2 clock
  clk: stm32mp1: fix SAI3 & SAI4 clocks
  clk: stm32mp1: remove unused dfsdm_src[] const
  clk: stm32mp1: add missing static

* clk-samsung:
  clk: samsung: simplify getting .drvdata

* clk-uniphier-mpeg:
  clk: uniphier: add LD11/LD20 stream demux system clock

* clk-stratix10:
  clk: socfpga: stratix10: suppress unbinding platform's clock driver
  clk: socfpga: stratix10: use platform driver APIs

* clk-aspeed:
  clk:aspeed: Fix reset bits for PCI/VGA and PECI
  clk: aspeed: Support second reset register

6 years agoMerge branches 'clk-qcom-rpmh', 'clk-npcm7xx', 'clk-of-parent-count' and 'clk-qcom...
Stephen Boyd [Mon, 4 Jun 2018 19:27:29 +0000 (12:27 -0700)]
Merge branches 'clk-qcom-rpmh', 'clk-npcm7xx', 'clk-of-parent-count' and 'clk-qcom-rcg-fix' into clk-next

* clk-qcom-rpmh:
  dt-bindings: clock: Introduce QCOM RPMh clock bindings

* clk-npcm7xx:
  clk: npcm7xx: fix return value check in npcm7xx_clk_init()
  clk: npcm7xx: add clock controller
  dt-binding: clk: npcm750: Add binding for Nuvoton NPCM7XX Clock

* clk-of-parent-count:
  pinctrl: sunxi: Use of_clk_get_parent_count() instead of open coding
  soc/tegra: pmc: Use of_clk_get_parent_count() instead of open coding
  soc: rockchip: power-domain: Use of_clk_get_parent_count() instead of open coding
  ARM: timer-sp: Use of_clk_get_parent_count() instead of open coding
  clk: Extract OF clock helpers in <linux/of_clk.h>

* clk-qcom-rcg-fix:
  clk: qcom: Base rcg parent rate off plan frequency

6 years agoMerge branch 'clk-actions' into clk-next
Stephen Boyd [Mon, 4 Jun 2018 19:27:02 +0000 (12:27 -0700)]
Merge branch 'clk-actions' into clk-next

* clk-actions:
  clk: actions: Add S900 SoC clock support
  clk: actions: Add pll clock support
  clk: actions: Add composite clock support
  clk: actions: Add fixed factor clock support
  clk: actions: Add factor clock support
  clk: actions: Add divider clock support
  clk: actions: Add mux clock support
  clk: actions: Add gate clock support
  clk: actions: Add common clock driver support
  dt-bindings: clock: Add Actions S900 clock bindings

6 years agoMerge branches 'clk-warn', 'clk-core', 'clk-spear' and 'clk-qcom-msm8998' into clk...
Stephen Boyd [Mon, 4 Jun 2018 19:26:39 +0000 (12:26 -0700)]
Merge branches 'clk-warn', 'clk-core', 'clk-spear' and 'clk-qcom-msm8998' into clk-next

* clk-warn:
  clk: Print the clock name and warning cause

* clk-core:
  clk: Remove clk_init_cb typedef

* clk-spear:
  clk: spear: fix WDT clock definition on SPEAr600

* clk-qcom-msm8998:
  clk: qcom: Add MSM8998 Global Clock Control (GCC) driver

6 years agoclk: qcom: Export clk_fabia_pll_configure()
Stephen Boyd [Sat, 2 Jun 2018 07:19:07 +0000 (00:19 -0700)]
clk: qcom: Export clk_fabia_pll_configure()

This is used by the video clk driver on sdm845 and that's a module.
Export it to prevent module build failures.

Signed-off-by: Stephen Boyd <sboyd@kernel.org>
6 years agoclk: bcm: Update and add Stingray clock entries
Pramod Kumar [Sat, 2 Jun 2018 00:56:07 +0000 (17:56 -0700)]
clk: bcm: Update and add Stingray clock entries

Update and add Stingray clock definitions and tables so they match the
binding document and the latest ASIC datasheet

Signed-off-by: Pramod Kumar <pramod.kumar@broadcom.com>
Signed-off-by: Ray Jui <ray.jui@broadcom.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
6 years agodt-bindings: clk: Update Stingray binding doc
Pramod Kumar [Sat, 2 Jun 2018 00:56:06 +0000 (17:56 -0700)]
dt-bindings: clk: Update Stingray binding doc

Update Stingray clock binding document to add additional clock entries
with names matching the latest ASIC datasheet. Also modify a few existing
entries to make their naming more consistent with the rest of the entries

Signed-off-by: Pramod Kumar <pramod.kumar@broadcom.com>
Signed-off-by: Ray Jui <ray.jui@broadcom.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
6 years agoclk-si544: Properly round requested frequency to nearest match
Mike Looijmans [Thu, 31 May 2018 14:03:55 +0000 (16:03 +0200)]
clk-si544: Properly round requested frequency to nearest match

The si544 driver had a rounding problem that using the result of clk_round_rate
may set the clock to yet another rate, for example:
clk_round_rate(195000000) = 194999999
clk_round_rate(194999999) = 194999998

Clients would expect that after clk_set_rate(clk, freq2=clk_round_rate(clk, freq)) the
chip will be running at exactly freq2.

The problem was in the calculation of the feedback divider, it was always rounded
down instead of to the nearest possible VCO value.

After this change, the following holds true for any supported frequency:
actual_freq = clk_round_rate(clk, freq);
clk_set_rate(clk, actual_freq);
clk_round_rate(clk, actual_freq) == actual_freq && clk_get_rate(clk) == actual_freq

Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl>
Fixes: 953cc3e81170 ("clk: Add driver for the si544 clock generator chip")
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
6 years agoclk: ingenic: jz4770: Add 150us delay after enabling VPU clock
Paul Cercueil [Sun, 20 May 2018 16:31:17 +0000 (16:31 +0000)]
clk: ingenic: jz4770: Add 150us delay after enabling VPU clock

This is required, as we must not use the AHB1 bus before it is stable.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
6 years agoclk: ingenic: jz4770: Enable power of AHB1 bus after ungating VPU clock
Paul Cercueil [Sun, 20 May 2018 16:31:16 +0000 (16:31 +0000)]
clk: ingenic: jz4770: Enable power of AHB1 bus after ungating VPU clock

This was broken before, because the AHB1 bus was enabled before the VPU
clock was ungated, while it must be done afterwards.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
6 years agoclk: ingenic: jz4770: Modify C1CLK clock to disable CPU clock stop on idle
Paul Cercueil [Sun, 20 May 2018 16:31:15 +0000 (16:31 +0000)]
clk: ingenic: jz4770: Modify C1CLK clock to disable CPU clock stop on idle

When the main processor goes idle, by default its clock is stopped.
However, this also stops the clock of the co-processor.

Here, if the C1CLK clock is enabled, we disable this functionality.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
6 years agoclk: ingenic: jz4770: Change OTG from custom to standard gated clock
Paul Cercueil [Sun, 20 May 2018 16:31:14 +0000 (16:31 +0000)]
clk: ingenic: jz4770: Change OTG from custom to standard gated clock

We now have the means to express the specificities of the OTG clock with
the common CGU code.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
6 years agoclk: ingenic: Support specifying "wait for clock stable" delay
Paul Cercueil [Sun, 20 May 2018 16:31:13 +0000 (16:31 +0000)]
clk: ingenic: Support specifying "wait for clock stable" delay

Some clocks need a small delay after being ungated to run stable, as
using them too soon might result in hardware lockups.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
6 years agoclk: ingenic: Add support for clocks whose gate bit is inverted
Paul Cercueil [Sun, 20 May 2018 16:31:12 +0000 (16:31 +0000)]
clk: ingenic: Add support for clocks whose gate bit is inverted

Support the clocks which are gated when their gate bit is cleared
instead of set.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
6 years agoclk: use match_string() helper
Yisheng Xie [Thu, 31 May 2018 11:11:14 +0000 (19:11 +0800)]
clk: use match_string() helper

match_string() returns the index of an array for a matching string,
which can be used instead of open coded variant.

Cc: Michael Turquette <mturquette@baylibre.com>
Cc: linux-clk@vger.kernel.org
Signed-off-by: Yisheng Xie <xieyisheng1@huawei.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
6 years agoclk: bcm2835: use match_string() helper
Yisheng Xie [Thu, 31 May 2018 11:11:13 +0000 (19:11 +0800)]
clk: bcm2835: use match_string() helper

match_string() returns the index of an array for a matching string,
which can be used instead of open coded variant.

Reviewed-by: Eric Anholt <eric@anholt.net>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Eric Anholt <eric@anholt.net>
Cc: Stefan Wahren <stefan.wahren@i2se.com>
Cc: linux-clk@vger.kernel.org
Cc: linux-rpi-kernel@lists.infradead.org
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: Yisheng Xie <xieyisheng1@huawei.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
6 years agoclk: Return void from debug_init op
Stephen Boyd [Sat, 2 Jun 2018 04:42:07 +0000 (21:42 -0700)]
clk: Return void from debug_init op

We only have two users of the debug_init hook, and we recently stopped
caring about the return value from that op. Finish that off by changing
the clk_op to return void instead of int because it doesn't matter if
debugfs fails or not.

Cc: Eric Anholt <eric@anholt.net>
Cc: David Lechner <david@lechnology.com>
Cc: Sekhar Nori <nsekhar@ti.com>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
6 years agoclk: remove clk_debugfs_add_file()
Greg Kroah-Hartman [Tue, 29 May 2018 16:08:04 +0000 (18:08 +0200)]
clk: remove clk_debugfs_add_file()

No one was using this api call, so remove it.  If it is ever needed in
the future, a "raw" debugfs call can be used.

Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
6 years agoclk: tegra: no need to check return value of debugfs_create functions
Greg Kroah-Hartman [Tue, 29 May 2018 16:08:03 +0000 (18:08 +0200)]
clk: tegra: no need to check return value of debugfs_create functions

When calling debugfs functions, there is no need to ever check the
return value.  The function can work or not, but the code logic should
never do something different based on this.

The return value of these functions were never checked in the end
anyway, so it is obvious this does not change any functionality :)

Cc: Peter De Schrijver <pdeschrijver@nvidia.com>
Cc: Prashant Gaikwad <pgaikwad@nvidia.com>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: Jonathan Hunter <jonathanh@nvidia.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
6 years agoclk: davinci: no need to check return value of debugfs_create functions
Greg Kroah-Hartman [Tue, 29 May 2018 16:08:02 +0000 (18:08 +0200)]
clk: davinci: no need to check return value of debugfs_create functions

When calling debugfs functions, there is no need to ever check the
return value.  The function can work or not, but the code logic should
never do something different based on this.

Acked-by: David Lechner <david@lechnology.com>
Cc: Sekhar Nori <nsekhar@ti.com>
Cc: Michael Turquette <mturquette@baylibre.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
6 years agoclk: bcm2835: no need to check return value of debugfs_create functions
Greg Kroah-Hartman [Tue, 29 May 2018 16:08:01 +0000 (18:08 +0200)]
clk: bcm2835: no need to check return value of debugfs_create functions

When calling debugfs functions, there is no need to ever check the
return value.  The function can work or not, but the code logic should
never do something different based on this.

Cc: Michael Turquette <mturquette@baylibre.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Cc: Stefan Wahren <stefan.wahren@i2se.com>
Cc: Florian Fainelli <f.fainelli@gmail.com>
Cc: Ray Jui <rjui@broadcom.com>
Cc: Scott Branden <sbranden@broadcom.com>
Cc: bcm-kernel-feedback-list@broadcom.com
Cc: Phil Elwell <phil@raspberrypi.org>
Cc: Boris Brezillon <boris.brezillon@bootlin.com>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Danilo Krummrich <danilokrummrich@dk-develop.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
6 years agoclk: no need to check return value of debugfs_create functions
Greg Kroah-Hartman [Tue, 29 May 2018 16:08:00 +0000 (18:08 +0200)]
clk: no need to check return value of debugfs_create functions

When calling debugfs functions, there is no need to ever check the
return value.  The function can work or not, but the code logic should
never do something different based on this.

This cleans up the init code a lot, and there's no need to return an
error value based on the debugfs calls, especially as it turns out no
one was even looking at that return value.  So it obviously wasn't that
important :)

Cc: Michael Turquette <mturquette@baylibre.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
6 years agoclk: imx6: add EPIT clock support
Colin Didier [Tue, 29 May 2018 17:04:33 +0000 (19:04 +0200)]
clk: imx6: add EPIT clock support

Add EPIT clock support to the i.MX6Q clocking infrastructure.

Signed-off-by: Colin Didier <colin.didier@devialet.com>
Signed-off-by: Clément Peron <clement.peron@devialet.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
6 years agoclk: mvebu: use correct bit for 98DX3236 NAND
Chris Packham [Thu, 24 May 2018 05:23:41 +0000 (17:23 +1200)]
clk: mvebu: use correct bit for 98DX3236 NAND

The correct fieldbit value for the NAND PLL reload trigger is 27.

Fixes: commit e120c17a70e5 ("clk: mvebu: support for 98DX3236 SoC")
Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
6 years agoclk/driver/hisi: Consolidate the Kconfig for the CLOCK_STUB
Daniel Lezcano [Tue, 22 May 2018 20:45:28 +0000 (22:45 +0200)]
clk/driver/hisi: Consolidate the Kconfig for the CLOCK_STUB

The current defconfig is inconsistent as it selects the mailbox and
the clock for the hi6220 and the hi3660 without having their Kconfigs
making sure the dependencies are correct. It ends up when selecting
different versions for the kernel (for example when git bisecting)
those options disappear and they don't get back, leading to unexpected
behaviors. In our case, the cpufreq driver does no longer work because
the clock fails to initialize due to the clock stub and the mailbox
missing.

In order to have the dependencies correctly set when defaulting, let's
do the same as commit 3a49afb84ca074e ("clk: enable hi655x common clk
automatically") where we select automatically the driver when the
parent driver is selected. With sensible defaults in place, we can leave
other choices for EXPERT.

Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Leo Yan <leo.yan@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
6 years agoclk: imx7d: reset parent for mipi csi root
Rui Miguel Silva [Tue, 22 May 2018 14:52:37 +0000 (15:52 +0100)]
clk: imx7d: reset parent for mipi csi root

To guarantee that we do not get Overflow in image FIFO the outer bandwidth has
to be faster than inputer bandwidth. For that it must be possible to set a
faster frequency clock. So set new parent to sys_pfd3 clock for the mipi csi
block.

Acked-by: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
6 years agoclk: imx7d: fix mipi dphy div parent
Rui Miguel Silva [Tue, 22 May 2018 14:52:36 +0000 (15:52 +0100)]
clk: imx7d: fix mipi dphy div parent

Fix the mipi dphy root divider to mipi_dphy_pre_div, this would remove a orphan
clock and set the correct parent.

before:
cat clk_orphan_summary
                                 enable  prepare  protect
   clock                          count    count    count        rate   accuracy   phase
----------------------------------------------------------------------------------------
 mipi_dphy_post_div                   1        1        0           0          0 0
    mipi_dphy_root_clk                1        1        0           0          0 0

cat clk_dump | grep mipi_dphy
mipi_dphy_post_div                    1        1        0           0          0 0
    mipi_dphy_root_clk                1        1        0           0          0 0

after:
cat clk_dump | grep mipi_dphy
   mipi_dphy_src                     1        1        0    24000000          0 0
       mipi_dphy_cg                  1        1        0    24000000          0 0
          mipi_dphy_pre_div          1        1        0    24000000          0 0
             mipi_dphy_post_div      1        1        0    24000000          0 0
                mipi_dphy_root_clk   1        1        0    24000000          0 0

Fixes: 8f6d8094b215 ("ARM: imx: add imx7d clk tree support")
Acked-by: Dong Aisheng <Aisheng.dong@nxp.com>
Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
6 years agoclk: qcom: gcc-msm8996: Disable halt check on UFS clocks
Bjorn Andersson [Thu, 24 May 2018 21:37:35 +0000 (14:37 -0700)]
clk: qcom: gcc-msm8996: Disable halt check on UFS clocks

The halt check of the UFS symbol clocks always fails, as such probing
UFS after clk_disable_unused always fails. This makes it impossible to
boot a system with the UFS phy or UFS HCD drivers compiled as modules.

Follow SDM845 and disable the halt check on these clocks.

Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
6 years agoclk: aspeed: Add 24MHz fixed clock
Lei YU [Fri, 18 May 2018 08:57:02 +0000 (16:57 +0800)]
clk: aspeed: Add 24MHz fixed clock

Add a 24MHz fixed clock.
This clock will be used for certain devices, e.g. pwm.

Signed-off-by: Lei YU <mine260309@gmail.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
6 years agoARM: dts: imx7: correct enet ipg clock
Anson Huang [Fri, 18 May 2018 01:01:06 +0000 (09:01 +0800)]
ARM: dts: imx7: correct enet ipg clock

ENET "ipg" clock should be IMX7D_ENETx_IPG_ROOT_CLK
rather than IMX7D_ENET_AXI_ROOT_CLK which is for ENET bus
clock.

Based on Andy Duan's patch from the NXP kernel tree.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
6 years agoclk: imx7d: correct enet clock CCGR registers
Anson Huang [Fri, 18 May 2018 01:01:05 +0000 (09:01 +0800)]
clk: imx7d: correct enet clock CCGR registers

Correct enet clock gates as below:

CCGR6: IMX7D_ENET_AXI_ROOT_CLK (enet1 and enet2 bus clocks)
CCGR112: IMX7D_ENET1_TIME_ROOT_CLK, IMX7D_ENET1_IPG_ROOT_CLK
CCGR113: IMX7D_ENET2_TIME_ROOT_CLK, IMX7D_ENET2_IPG_ROOT_CLK

Just rename unused IMX7D_ENETx_REF_ROOT_CLK for
IMX7D_ENETx_IPG_ROOT_CLK instead of adding new clocks.

Based on Andy Duan's patch from the NXP kernel tree.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
6 years agoclk: imx7d: correct enet phy ref clock gates
Anson Huang [Fri, 18 May 2018 01:01:04 +0000 (09:01 +0800)]
clk: imx7d: correct enet phy ref clock gates

IMX7D_ENET_PHY_REF_ROOT_DIV supplies clock for PHY directly,
there is no clock gate after it, rename it to
IMX7D_ENET_PHY_REF_ROOT_CLK to avoid device tree change.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
6 years agoclk: imx6sl: correct ocram_podf clock type
Anson Huang [Thu, 17 May 2018 05:00:48 +0000 (13:00 +0800)]
clk: imx6sl: correct ocram_podf clock type

IMX6SL_CLK_OCRAM_PODF is a busy divider, its name in
CCM_CDHIPR register of Reference Manual CCM chapter
is axi_podf_busy, correct its clock type.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Acked-by: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
6 years agoclk: imx6sx: disable unnecessary clocks during clock initialization
Anson Huang [Thu, 17 May 2018 05:00:47 +0000 (13:00 +0800)]
clk: imx6sx: disable unnecessary clocks during clock initialization

Disable those unnecessary clocks during kernel boot up to save power,
those modules clock should be managed by modules driver in runtime.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Acked-by: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
6 years agoclk: qcom: Add video clock controller driver for SDM845
Amit Nischal [Wed, 9 May 2018 11:32:31 +0000 (17:02 +0530)]
clk: qcom: Add video clock controller driver for SDM845

Add support for the video clock controller found on SDM845
based devices. This would allow video drivers to probe and
control their clocks.

Signed-off-by: Amit Nischal <anischal@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
6 years agodt-bindings: clock: Introduce QCOM Video clock bindings
Amit Nischal [Wed, 9 May 2018 11:32:30 +0000 (17:02 +0530)]
dt-bindings: clock: Introduce QCOM Video clock bindings

Add device tree bindings for video clock controller for
Qualcomm Technology Inc's SoCs.

Signed-off-by: Amit Nischal <anischal@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
6 years agoclk: msm8996-gcc: Mark halt check as no-op for USB/PCIE pipe_clk
Manu Gautam [Wed, 2 May 2018 21:06:08 +0000 (02:36 +0530)]
clk: msm8996-gcc: Mark halt check as no-op for USB/PCIE pipe_clk

The USB and PCIE pipe clocks are sourced from external clocks
inside the QMP USB/PCIE PHYs. Enabling or disabling of PIPE RCG
clocks is dependent on PHY initialization sequence hence
update halt_check to BRANCH_HALT_SKIP for these clocks so
that clock status bit is not polled when enabling or disabling
the clocks. It allows to simplify PHY client driver code which
is both user and source of the pipe_clk and avoid error logging
related status check on clk_disable/enable.

Signed-off-by: Manu Gautam <mgautam@codeaurora.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
6 years agoclk: qcom: mmcc-msm8996: leave all mmagic gdscs and clocks always enabled
Rajendra Nayak [Fri, 23 Mar 2018 08:26:16 +0000 (13:56 +0530)]
clk: qcom: mmcc-msm8996: leave all mmagic gdscs and clocks always enabled

There's no bus infrastructure today to handle all the mmagic bus
clocks and GDSCs needed by all the multimedia blocks in msm8996, like
mdss, video, camera and gpu. Mark all these clocks with a CLK_IS_CRITICAL
and GDSCs with a ALWAYS_ON flag for now so they are left always enabled.
This patch should be reverted at some point when we do have a bus driver
to manage these clocks and GDSCs.

Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
6 years agoclk: qcom: Register the gdscs before the clocks
Rajendra Nayak [Fri, 23 Mar 2018 08:26:15 +0000 (13:56 +0530)]
clk: qcom: Register the gdscs before the clocks

We have atleast some instances of ALWAYS_ON gdscs, which need to
be turned ON *before* some clocks within the gdsc domain marked
with a CLK_IS_CRITICAL can be turned ON.
To facilitate this sequence, register the GDCSs (and hence handle
the ALWAYS_ON gdscs) before we register clocks (and handle the
clocks marked as CLK_IS_CRITICAL)

Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Tested-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
6 years agoclk: qcom: gdsc: Add support for ALWAYS_ON gdscs
Rajendra Nayak [Fri, 23 Mar 2018 08:26:14 +0000 (13:56 +0530)]
clk: qcom: gdsc: Add support for ALWAYS_ON gdscs

Some GDSCs might have software control to turn them off, but we might
want to keep them enabled always, in some cases because of lack of
support in kernel to handle a graceful turning off/on of such GDSCs.
Most common instances would be the GDCSs which power up the noc/bus
fabrics, which need bus drivers to handle them and atleast support for
which is missing on all qcom SoCs.

Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Tested-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
6 years agoclk: berlin: switch to SPDX license identifier
Jisheng Zhang [Wed, 16 May 2018 08:04:29 +0000 (16:04 +0800)]
clk: berlin: switch to SPDX license identifier

Use the appropriate SPDX license identifier and drop the previous
license text.

Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
6 years agoMerge tag 'tegra-for-4.18-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra...
Stephen Boyd [Fri, 1 Jun 2018 17:27:58 +0000 (10:27 -0700)]
Merge tag 'tegra-for-4.18-clk' of git://git./linux/kernel/git/tegra/linux into clk-tegra

Pull Tegra clk driver updates from Thierry Reding:

 - proper implementation of the CDEV1/2 clocks on Tegra20

* tag 'tegra-for-4.18-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  clk: tegra: Add quirk for getting CDEV1/2 clocks on Tegra20
  clk: tegra20: Correct parents of CDEV1/2 clocks
  clk: tegra20: Add DEV1/DEV2 OSC dividers

6 years agoMerge tag 'v4.18-rockchip-clk-1' of git://git.kernel.org/pub/scm/linux/kernel/git...
Stephen Boyd [Fri, 1 Jun 2018 17:26:06 +0000 (10:26 -0700)]
Merge tag 'v4.18-rockchip-clk-1' of git://git./linux/kernel/git/mmind/linux-rockchip into clk-rockchip

Pull rockchip clk driver updates from Heiko Stuebner:

Conversion to match_string helper of open-coded string comparison
and removal of the initial devicetree-based gate-clocks, which were
deprecated since 2014.

* tag 'v4.18-rockchip-clk-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  clk: rockchip: remove deprecated gate-clk code and dt-binding
  clk: rockchip: use match_string() helper

6 years agoMerge tag 'sunxi-clk-for-4.18' of https://git.kernel.org/pub/scm/linux/kernel/git...
Stephen Boyd [Fri, 1 Jun 2018 17:22:25 +0000 (10:22 -0700)]
Merge tag 'sunxi-clk-for-4.18' of https://git./linux/kernel/git/sunxi/linux into clk-allwinner

Pull Allwinner clock changes from Maxime Ripard:

Not a lot of changes for this release, but two quite important features
were added: the H6 PRCM clock support, and the needed changes to the R40
clock driver to allow for the EMAC to operate.

* tag 'sunxi-clk-for-4.18' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
  clk: sunxi-ng: r40: export a regmap to access the GMAC register
  clk: sunxi-ng: r40: rewrite init code to a platform driver
  clk: sunxi-ng: add support for H6 PRCM CCU

6 years agoMerge tag 'meson-clk-4.18-2' of https://github.com/BayLibre/clk-meson into clk-meson
Stephen Boyd [Fri, 1 Jun 2018 17:17:54 +0000 (10:17 -0700)]
Merge tag 'meson-clk-4.18-2' of https://github.com/BayLibre/clk-meson into clk-meson

Pull Second round of update for meson clocks from Jerome Brunet:

 - Add critical flag to meson8b's fdiv2 as temporary fixup for the ethernet.
 - Clean up license headers with SPDX
 - Add round closest support to mpll driver.

* tag 'meson-clk-4.18-2' of https://github.com/BayLibre/clk-meson:
  clk: meson: axg: let mpll clocks round closest
  clk: meson: mpll: add round closest support
  clk: meson: meson8b: mark fclk_div2 gate clocks as CLK_IS_CRITICAL
  clk: meson: use SPDX license identifiers consistently

6 years agoclk: davinci: Fix link errors when not all SoCs are enabled
David Lechner [Fri, 25 May 2018 18:11:50 +0000 (13:11 -0500)]
clk: davinci: Fix link errors when not all SoCs are enabled

This fixes linker errors due to undefined symbols when one or more of
the TI DaVinci SoCs is not enabled in the kernel config.

Signed-off-by: David Lechner <david@lechnology.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/20180525181150.17873-10-david@lechnology.com

6 years agoclk: davinci: psc: allow for dev == NULL
David Lechner [Fri, 25 May 2018 18:11:49 +0000 (13:11 -0500)]
clk: davinci: psc: allow for dev == NULL

On some davinci SoCs, we need to register the PSC clocks during early
boot because they are needed for clocksource/clockevent. These changes
allow for dev == NULL because in this case, we won't have a platform
device for the clocks.

Signed-off-by: David Lechner <david@lechnology.com>
Reviewed-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/20180525181150.17873-9-david@lechnology.com

6 years agoclk: davinci: da850-pll: change PLL0 to CLK_OF_DECLARE
David Lechner [Fri, 25 May 2018 18:11:48 +0000 (13:11 -0500)]
clk: davinci: da850-pll: change PLL0 to CLK_OF_DECLARE

PLL0 on davinci/da850-type device needs to be registered early in boot
because it is needed for clocksource/clockevent. Change the driver
to use CLK_OF_DECLARE for this special case.

Reviewed-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: David Lechner <david@lechnology.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/20180525181150.17873-8-david@lechnology.com

6 years agoclk: davinci: pll: allow dev == NULL
David Lechner [Fri, 25 May 2018 18:11:47 +0000 (13:11 -0500)]
clk: davinci: pll: allow dev == NULL

This modifies the TI Davinci PLL clock driver to allow for the case
when dev == NULL. On some (most) SoCs that use this driver, the PLL
clock needs to be registered during early boot because it is used
for clocksource/clkevent and there will be no platform device available.

Signed-off-by: David Lechner <david@lechnology.com>
Reviewed-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/20180525181150.17873-7-david@lechnology.com

6 years agoclk: davinci: psc-dm365: fix few clocks
Sekhar Nori [Fri, 25 May 2018 18:11:46 +0000 (13:11 -0500)]
clk: davinci: psc-dm365: fix few clocks

Fix parent of EMAC and voice codec PSC clocks. Documentation is clear
on EMAC clock parent, but its not fully clear on parent of voice codec
clock. The implementation chosen is matches arch/arm/mach-davinci/dm365.c.
Add a comment explaining this for posterity.

There is only one power domain on DM365. Fix the power domain of voice
codec and vpss dac modules.

While at it, add a comment explaining how the parent of vpss dac clock was
derived. Note that this patch does not touch the parent of vpss dac clock.

Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Reviewed-by: David Lechner <david@lechnology.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/20180525181150.17873-6-david@lechnology.com

6 years agoclk: davinci: pll-dm646x: keep PLL2 SYSCLK1 always enabled
Sekhar Nori [Fri, 25 May 2018 18:11:45 +0000 (13:11 -0500)]
clk: davinci: pll-dm646x: keep PLL2 SYSCLK1 always enabled

PLL2 SYSCLK1 on DM646x is connected to DDR2 PHY and cannot
be disabled. Mark it so to prevent unused clock disable
infrastructure from disabling it.

Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Reviewed-by: David Lechner <david@lechnology.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/20180525181150.17873-5-david@lechnology.com

6 years agoclk: davinci: psc-dm355: fix ASP0/1 clkdev lookups
David Lechner [Fri, 25 May 2018 18:11:44 +0000 (13:11 -0500)]
clk: davinci: psc-dm355: fix ASP0/1 clkdev lookups

The clkdev lookups for the ASP0/1 devices on TI DM355 were declared, but
not assigned to any LPSC. This assigns the clkdev lookups to the
correct LPSCs.

Reported-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: David Lechner <david@lechnology.com>
Reviewed-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/20180525181150.17873-4-david@lechnology.com

6 years agoclk: davinci: pll-dm355: fix SYSCLKn parent names
David Lechner [Fri, 25 May 2018 18:11:43 +0000 (13:11 -0500)]
clk: davinci: pll-dm355: fix SYSCLKn parent names

This fixes the parent clock names of the SYSCLKn clocks for the DM355
SoC in the TI DaVinici PLL clock driver.

It appears that this name just didn't get updated to the correct name
like the other SoCs during the driver's development.

Reported-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: David Lechner <david@lechnology.com>
Acked-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/20180525181150.17873-3-david@lechnology.com

6 years agoclk: davinci: pll-dm355: drop pll2_sysclk2
David Lechner [Fri, 25 May 2018 18:11:42 +0000 (13:11 -0500)]
clk: davinci: pll-dm355: drop pll2_sysclk2

This removes pll2_sysclk2 from the TI DM355 clock driver. This SoC
doesn't have such a clock. Also, SYSCLK_ALWAYS_ENABLED is transferred
to pll2_sysclk1 since it drives the DDR and doesn't have another
mechanism to keep it on.

Reported-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: David Lechner <david@lechnology.com>
Acked-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/20180525181150.17873-2-david@lechnology.com

7 years agoclk: rockchip: remove deprecated gate-clk code and dt-binding
Heiko Stuebner [Sat, 12 May 2018 14:30:38 +0000 (16:30 +0200)]
clk: rockchip: remove deprecated gate-clk code and dt-binding

Initially we tried modeling clocks via the devicetree before switching
to clocks declared in the clock drivers and only exporting specific
ids to the devicetree.

As the old code was in the kernel for 1-2 releases when the new mode
of operation was added we kept it for backwards compatibility.

That deprecation notice is in the binding since july 2014, so nearly
4 years now and I think it's time to drop the old cruft.

Especially as at the time using the mainline kernel on Rockchip devices
was not really possible, except for experiments on the really old socs of
the rk3066 + rk3188 line, so there shouldn't be any devicetrees still
around that rely on that code.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Reviewed-by: Rob Herring <robh@kernel.org>
7 years agoclk: rockchip: use match_string() helper
Yisheng Xie [Mon, 21 May 2018 11:57:50 +0000 (19:57 +0800)]
clk: rockchip: use match_string() helper

match_string() returns the index of an array for a matching string,
which can be used intead of open coded variant.

Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Heiko Stuebner <heiko@sntech.de>
Cc: linux-clk@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-rockchip@lists.infradead.org
Signed-off-by: Yisheng Xie <xieyisheng1@huawei.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
7 years agoclk: meson: axg: let mpll clocks round closest
Jerome Brunet [Tue, 15 May 2018 16:36:52 +0000 (18:36 +0200)]
clk: meson: axg: let mpll clocks round closest

Let the mpll dividers achieve the closest rate possible, even if
it means rounding the requested rate up.

This is done to improve the accuracy of the rates provided by these
plls to the audio subsystem

Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
7 years agoclk: meson: mpll: add round closest support
Jerome Brunet [Tue, 15 May 2018 16:36:51 +0000 (18:36 +0200)]
clk: meson: mpll: add round closest support

Allow the mpll driver to round the requested rate up if
CLK_MESON_MPLL_ROUND_CLOSEST is set and it provides a rate closer to the
requested rate.

Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Martin Blumenstingl<martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
7 years agoclk: meson: meson8b: mark fclk_div2 gate clocks as CLK_IS_CRITICAL
Martin Blumenstingl [Sun, 20 May 2018 17:16:06 +0000 (19:16 +0200)]
clk: meson: meson8b: mark fclk_div2 gate clocks as CLK_IS_CRITICAL

Until commit 05f814402d6174 ("clk: meson: add fdiv clock gates") we
relied on the bootloader to enable the fclk_div clock gates. It turns
out that our clock tree is incomplete at least on Meson8b (tested with
an Odroid-C1, which uses an RGMII PHY) because after the mentioned
commit Ethernet is not working anymore (no RX/TX activity can be seen).
At the same time Ethernet was still working on Meson8m2 with a RMII PHY.

Testing has shown that as soon as "fclk_div2" is disabled Ethernet stops
working on Odroid-C1. Unfortunately it's currently not clear what the
Ethernet controller IP block uses the fclk_div2 clock for. Mark the
clock as CLK_IS_CRITICAL to keep it enabled (as it's already enabled by
most bootloaders by default, which is why we didn't notice it before).

Fixes: 05f814402d6174 ("clk: meson: add fdiv clock gates")
Cc: stable@vger.kernel.org
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Tested-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
7 years agoclk: tegra: Add quirk for getting CDEV1/2 clocks on Tegra20
Dmitry Osipenko [Tue, 8 May 2018 16:26:06 +0000 (19:26 +0300)]
clk: tegra: Add quirk for getting CDEV1/2 clocks on Tegra20

CDEV1 and CDEV2 clocks are a bit special case, their parent clock is
created by the pinctrl driver. It should be possible for clk user to
request these clocks before pinctrl driver got probed and hence user will
get an orphaned clock. That might be undesirable because user may expect
parent clock to be enabled by the child, so let's return -EPROBE_DEFER
till parent clock appears.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
7 years agoclk: tegra20: Correct parents of CDEV1/2 clocks
Dmitry Osipenko [Tue, 8 May 2018 16:26:05 +0000 (19:26 +0300)]
clk: tegra20: Correct parents of CDEV1/2 clocks

Parents of CDEV1/2 clocks are determined by muxing of the corresponding
pins. Pinctrl driver now provides the CDEV1/2 clock muxes and hence
CDEV1/2 clocks could have correct parents. Set CDEV1/2 parents to the
corresponding muxes to fix the parents.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Reviewed-by: Marcel Ziswiler <marcel@ziswiler.com>
Tested-by: Marcel Ziswiler <marcel@ziswiler.com>
Tested-by: Marc Dietrich <marvin24@gmx.de>
Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
7 years agoclk: tegra20: Add DEV1/DEV2 OSC dividers
Dmitry Osipenko [Tue, 8 May 2018 16:26:03 +0000 (19:26 +0300)]
clk: tegra20: Add DEV1/DEV2 OSC dividers

CDEV1/CDEV2 clocks could have corresponding oscillator clock divider as
a parent. Add these dividers in order to be able to provide that parent
option.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Reviewed-by: Marcel Ziswiler <marcel@ziswiler.com>
Tested-by: Marcel Ziswiler <marcel@ziswiler.com>
Tested-by: Marc Dietrich <marvin24@gmx.de>
Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
7 years agoclk: meson: use SPDX license identifiers consistently
Jerome Brunet [Wed, 16 May 2018 08:50:40 +0000 (10:50 +0200)]
clk: meson: use SPDX license identifiers consistently

Replace every license notices in drivers/clk/meson by SPDX license
identifiers, as described in license-rules.rst

Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
7 years agoclk: sunxi-ng: r40: export a regmap to access the GMAC register
Icenowy Zheng [Tue, 1 May 2018 16:12:14 +0000 (00:12 +0800)]
clk: sunxi-ng: r40: export a regmap to access the GMAC register

There's a GMAC configuration register, which exists on A64/A83T/H3/H5 in
the syscon part, in the CCU of R40 SoC.

Export a regmap of the CCU.

Read access is not restricted to all registers, but only the GMAC
register is allowed to be written.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
7 years agoclk: sunxi-ng: r40: rewrite init code to a platform driver
Icenowy Zheng [Tue, 1 May 2018 16:12:13 +0000 (00:12 +0800)]
clk: sunxi-ng: r40: rewrite init code to a platform driver

As we need to register a regmap on the R40 CCU, there needs to be a
device structure bound to the CCU device node.

Rewrite the R40 CCU driver initial code to make it a proper platform
driver, thus we will have a platform device bound to it.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
7 years agoclk: at91: PLL recalc_rate() now using cached MUL and DIV values
Marcin Ziemianowicz [Sun, 29 Apr 2018 19:01:11 +0000 (15:01 -0400)]
clk: at91: PLL recalc_rate() now using cached MUL and DIV values

When a USB device is connected to the USB host port on the SAM9N12 then
you get "-62" error which seems to indicate USB replies from the device
are timing out. Based on a logic sniffer, I saw the USB bus was running
at half speed.

The PLL code uses cached MUL and DIV values which get set in set_rate()
and applied in prepare(), but the recalc_rate() function instead
queries the hardware instead of using these cached values. Therefore,
if recalc_rate() is called between a set_rate() and prepare(), the
wrong frequency is calculated and later the USB clock divider for the
SAM9N12 SOC will be configured for an incorrect clock.

In my case, the PLL hardware was set to 96 Mhz before the OHCI
driver loads, and therefore the usb clock divider was being set
to /2 even though the OHCI driver set the PLL to 48 Mhz.

As an alternative explanation, I noticed this was fixed in the past by
87e2ed338f1b ("clk: at91: fix recalc_rate implementation of PLL
driver") but the bug was later re-introduced by 1bdf02326b71 ("clk:
at91: make use of syscon/regmap internally").

Fixes: 1bdf02326b71 ("clk: at91: make use of syscon/regmap internally)
Cc: <stable@vger.kernel.org>
Signed-off-by: Marcin Ziemianowicz <marcin@ziemianowicz.com>
Acked-by: Boris Brezillon <boris.brezillon@bootlin.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
7 years agoMerge tag 'meson-clk-4.18-1' of https://github.com/BayLibre/clk-meson into clk-meson
Stephen Boyd [Tue, 15 May 2018 22:49:49 +0000 (15:49 -0700)]
Merge tag 'meson-clk-4.18-1' of https://github.com/BayLibre/clk-meson into clk-meson

Pull meson clk driver updates from Jerome Brunet:

 - Add meson8b nand clocks
 - Add gxbb video decoder clocks
 - Rework of gxbb AO clock controller code to allow code reuse
 - Add axg AO clock controller

A rework of the AO clock controller found on the gxbb SoC family has
been done to improve code re-usability before introducing a very similar
controller for the axg SoC family.

* tag 'meson-clk-4.18-1' of https://github.com/BayLibre/clk-meson:
  clk: meson: drop CLK_SET_RATE_PARENT flag
  clk: meson-axg: Add AO Clock and Reset controller driver
  clk: meson: aoclk: refactor common code into dedicated file
  clk: meson: migrate to devm_of_clk_add_hw_provider API
  clk: meson: gxbb: add the video decoder clocks
  clk: meson: meson8b: add support for the NAND clocks
  dt-bindings: clock: reset: Add AXG AO Clock and Reset Bindings
  dt-bindings: clock: axg-aoclkc: New binding for Meson-AXG SoC
  clk: meson: gxbb: expose VDEC_1 and VDEC_HEVC clocks
  dt-bindings: clock: meson8b: export the NAND clock

7 years agoMerge tag 'clk-renesas-for-v4.18-tag1' of git://git.kernel.org/pub/scm/linux/kernel...
Stephen Boyd [Tue, 15 May 2018 22:36:41 +0000 (15:36 -0700)]
Merge tag 'clk-renesas-for-v4.18-tag1' of git://git./linux/kernel/git/geert/renesas-drivers into clk-renesas

Pull renesas clk driver updates from Geert Uytterhoeven:

  - Add support for the MSIOF module clocks on R-Car M3-N
  - Add support for the new RZ/G1C and R-Car E3 SoCs

* tag 'clk-renesas-for-v4.18-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
  clk: renesas: cpg-mssr: Add support for R-Car E3
  clk: renesas: Add r8a77990 CPG Core Clock Definitions
  clk: renesas: rcar-gen2: Centralize quirks handling
  clk: renesas: r8a77980: Correct parent clock of PCIEC0
  clk: renesas: r8a7794: Fix LB clock divider
  clk: renesas: r8a7792: Fix LB clock divider
  clk: renesas: r8a7791/r8a7793: Fix LB clock divider
  clk: renesas: r8a7745: Fix LB clock divider
  clk: renesas: r8a7743: Fix LB clock divider
  clk: renesas: cpg-mssr: Add r8a77470 support
  clk: renesas: Add r8a77470 CPG Core Clock Definitions
  clk: renesas: r8a77965: Add MSIOF controller clocks

7 years agoclk: davinci: psc-da830: fix USB0 48MHz PHY clock registration
Sekhar Nori [Mon, 7 May 2018 11:34:57 +0000 (17:04 +0530)]
clk: davinci: psc-da830: fix USB0 48MHz PHY clock registration

USB0 48MHz PHY clock registration fails on DA830 because the
da8xx-cfgchip clock driver cannot get a reference to USB0
LPSC clock.

The USB0 LPSC needs to be enabled during PHY clock enable. Setup
the clock lookup correctly to fix this.

Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Reviewed-by: David Lechner <david@lechnology.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
7 years agoclk: imx: Add new clo01 and clo2 controlled by CCOSR
Michael Trimarchi [Fri, 20 Apr 2018 21:00:04 +0000 (23:00 +0200)]
clk: imx: Add new clo01 and clo2 controlled by CCOSR

osc->cko2_sel->cko2_podf->clk_cko2->clk_cko

Example of usage to provide clock to the sgtl5000

codec: sgtl5000@0a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
clocks = <&clks IMX6UL_CLK_OSC>;
#sound-dai-cells = <0>;
clocks = <&clks IMX6UL_CLK_CKO>;
assigned-clocks = <&clks IMX6UL_CLK_CKO2_SEL>,
  <&clks IMX6UL_CLK_CKO2_PODF>,
  <&clks IMX6UL_CLK_CKO2>,
  <&clks IMX6UL_CLK_CKO>;
assigned-clock-parents = <&clks IMX6UL_CLK_OSC>,
 <&clks IMX6UL_CLK_CKO2_SEL>,
 <&clks IMX6UL_CLK_CKO2_PODF>,
 <&clks IMX6UL_CLK_CKO2>;
clock-names = "mclk";
wlf,shared-lrclk;

Signed-off-by: Matteo Lisi <matteo.lisi@engicam.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Tested-by: Michael Trimarchi <michael@amarulasolutions.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
7 years agoclk: mediatek: add g3dsys support for MT2701 and MT7623
Sean Wang [Fri, 27 Apr 2018 08:14:46 +0000 (16:14 +0800)]
clk: mediatek: add g3dsys support for MT2701 and MT7623

Add clock driver support for g3dsys on MT2701 and MT7623, which is
providing essential clock gate and reset controller to Mali-450.

Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
7 years agodt-bindings: reset: mediatek: add entry for Mali-450 node to refer
Sean Wang [Fri, 27 Apr 2018 08:14:45 +0000 (16:14 +0800)]
dt-bindings: reset: mediatek: add entry for Mali-450 node to refer

Just add binding for a required reset referenced by Mali-450 on MT7623
or MT2701 SoC.

Cc: devicetree@vger.kernel.org
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
7 years agodt-bindings: clock: mediatek: add entry for Mali-450 node to refer
Sean Wang [Fri, 27 Apr 2018 08:14:44 +0000 (16:14 +0800)]
dt-bindings: clock: mediatek: add entry for Mali-450 node to refer

Just add binding for a required clock referenced by Mali-450 on MT7623
or MT2701 SoC.

Cc: devicetree@vger.kernel.org
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
7 years agodt-bindings: clock: mediatek: add g3dsys bindings
Sean Wang [Fri, 27 Apr 2018 08:14:43 +0000 (16:14 +0800)]
dt-bindings: clock: mediatek: add g3dsys bindings

Add bindings to g3dsys providing necessary clock and reset control to
Mali-450.

Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
7 years agoclk: mediatek: correct the clocks for MT2701 HDMI PHY module
Ryder Lee [Tue, 17 Apr 2018 12:30:27 +0000 (20:30 +0800)]
clk: mediatek: correct the clocks for MT2701 HDMI PHY module

The hdmitx_dig_cts clock signal is not a child of clk26m,
and the actual output of the PLL block is derived from
the tvdpll via a configurable PLL post-divider.

It is used as the PLL reference input to the HDMI PHY module.

Fixes: e9862118272a ("clk: mediatek: Add MT2701 clock support")
Signed-off-by: Chunhui Dai <chunhui.dai@mediatek.com>
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
7 years agoclk: bulk: silently error out on EPROBE_DEFER
Jerome Brunet [Mon, 9 Apr 2018 14:13:03 +0000 (16:13 +0200)]
clk: bulk: silently error out on EPROBE_DEFER

In clk_bulk_get(), if we fail to get the clock due to probe deferal, we
shouldn't print an error message. Just be silent in this case.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
7 years agoclk: hisilicon: add missing usb3 clocks for Hi3798CV200 SoC
Jianguo Sun [Fri, 4 May 2018 08:56:30 +0000 (16:56 +0800)]
clk: hisilicon: add missing usb3 clocks for Hi3798CV200 SoC

There are two USB3 host controllers on Hi3798CV200 SoC.
This commit adds missing clocks for them.

Signed-off-by: Jianguo Sun <sunjianguo1@huawei.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
7 years agoclk:aspeed: Fix reset bits for PCI/VGA and PECI
Jae Hyun Yoo [Thu, 26 Apr 2018 17:22:32 +0000 (10:22 -0700)]
clk:aspeed: Fix reset bits for PCI/VGA and PECI

This commit fixes incorrect setting of reset bits for PCI/VGA and
PECI modules.

1. Reset bit for PCI/VGA is 8.
2. PECI reset bit is missing so added bit 10 as its reset bit.

Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>
Fixes: 15ed8ce5f84e ("clk: aspeed: Register gated clocks")
Cc: stable <stable@vger.kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
7 years agoclk: aspeed: Support second reset register
Joel Stanley [Fri, 27 Apr 2018 02:55:47 +0000 (12:25 +0930)]
clk: aspeed: Support second reset register

The ast2500 has an additional reset register that contains resets not
present in the ast2400. This enables support for this register, and adds
the one reset line that is controlled by it.

Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
7 years agoclk: socfpga: stratix10: suppress unbinding platform's clock driver
Dinh Nguyen [Wed, 2 May 2018 14:28:33 +0000 (09:28 -0500)]
clk: socfpga: stratix10: suppress unbinding platform's clock driver

The Stratix10 clock driver is essential to system operation, so their
removal should never happen.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
7 years agoclk: socfpga: stratix10: use platform driver APIs
Dinh Nguyen [Wed, 2 May 2018 14:28:32 +0000 (09:28 -0500)]
clk: socfpga: stratix10: use platform driver APIs

Use platform driver APIs to map memory so that it will automatically free
the memory in case of errors.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
[sboyd@kernel.org: Return -ENOMEM error pointers, check for error
pointer at call site]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
7 years agoclk: uniphier: add LD11/LD20 stream demux system clock
Katsuhiro Suzuki [Tue, 15 May 2018 02:14:16 +0000 (11:14 +0900)]
clk: uniphier: add LD11/LD20 stream demux system clock

Add clock for MPEG2 transport stream I/O and demux system (HSC) on
UniPhier LD11/LD20 SoCs.

Signed-off-by: Katsuhiro Suzuki <suzuki.katsuhiro@socionext.com>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
7 years agoclk: samsung: simplify getting .drvdata
Wolfram Sang [Thu, 19 Apr 2018 14:05:35 +0000 (16:05 +0200)]
clk: samsung: simplify getting .drvdata

We should get drvdata from struct device directly. Going via
platform_device is an unneeded step back and forth.

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
7 years agoclk: stm32mp1: Fix a memory leak in 'clk_stm32_register_gate_ops()'
Christophe JAILLET [Sun, 13 May 2018 11:17:04 +0000 (13:17 +0200)]
clk: stm32mp1: Fix a memory leak in 'clk_stm32_register_gate_ops()'

We allocate some memory which is neither used, nor referenced by anything.
So axe it.

Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Acked-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
7 years agoclk: stm32mp1: Add CLK_IGNORE_UNUSED to ck_sys_dbg clock
Gabriel Fernandez [Tue, 24 Apr 2018 07:58:43 +0000 (09:58 +0200)]
clk: stm32mp1: Add CLK_IGNORE_UNUSED to ck_sys_dbg clock

Don't disable the dbg clock if was set by bootloader.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
7 years agoclk: meson: drop CLK_SET_RATE_PARENT flag
Yixun Lan [Thu, 3 May 2018 13:26:24 +0000 (21:26 +0800)]
clk: meson: drop CLK_SET_RATE_PARENT flag

The clk81 is not expected to be changed, so drop this flag.

Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
7 years agoclk: meson-axg: Add AO Clock and Reset controller driver
Qiufang Dai [Thu, 3 May 2018 13:26:23 +0000 (21:26 +0800)]
clk: meson-axg: Add AO Clock and Reset controller driver

Adds a Clock and Reset controller driver for the Always-On part
of the Amlogic Meson-AXG SoC.

Signed-off-by: Qiufang Dai <qiufang.dai@amlogic.com>
Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
7 years agoclk: meson: aoclk: refactor common code into dedicated file
Yixun Lan [Thu, 3 May 2018 13:26:20 +0000 (21:26 +0800)]
clk: meson: aoclk: refactor common code into dedicated file

We try to refactor the common code into one dedicated file,
while preparing to add new Meson-AXG aoclk driver, this would
help us to better share the code by all aoclk drivers.

Suggested-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
7 years agoMerge branch 'next/bindings' into next/drivers
Jerome Brunet [Tue, 15 May 2018 12:19:32 +0000 (14:19 +0200)]
Merge branch 'next/bindings' into next/drivers

7 years agoclk: meson: migrate to devm_of_clk_add_hw_provider API
Yixun Lan [Thu, 26 Apr 2018 08:44:31 +0000 (16:44 +0800)]
clk: meson: migrate to devm_of_clk_add_hw_provider API

There is a protential memory leak, as of_clk_del_provider is
never called if of_clk_add_hw_provider has been executed.
Fix this by using devm variant API.

Fixes: f8c11f79912d ("clk: meson: Add GXBB AO Clock and Reset controller driver")
Suggested-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
7 years agoclk: meson: gxbb: add the video decoder clocks
Maxime Jourdan [Tue, 24 Apr 2018 18:48:38 +0000 (20:48 +0200)]
clk: meson: gxbb: add the video decoder clocks

Add the SEL/DIV/GATE for VDEC_1 and VDEC_HEVC.

Signed-off-by: Maxime Jourdan <maxi.jourdan@wanadoo.fr>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
7 years agoclk: meson: meson8b: add support for the NAND clocks
Martin Blumenstingl [Mon, 23 Apr 2018 19:35:09 +0000 (21:35 +0200)]
clk: meson: meson8b: add support for the NAND clocks

This adds the NAND clocks (from the HHI_NAND_CLK_CNTL register) to the
Meson8b clock driver. There are three NAND clocks: a gate which enables
or disables the NAND clock, a mux and a divider (which divides the mux
output).
Unfortunately the public S805 datasheet does not document the mux
parents. However, the vendor kernel has a few hints for us which allows
us to make an educated guess about the clock parents. To do this we need
to have a look at set_nand_core_clk() from the vendor's NAND driver (see
[0]):
- XTAL = (4<<9) | (1<<8) | 0
- 160MHz = (0<<9) | (1<<8) | 3)
- 182MHz = (3<<9) | (1<<8) | 1)
- 212MHz = (1<<9) | (1<<8) | 3)
- 255MHz = (2<<9) | (1<<8) | 1)

While there is a comment for the XTAL parent (which indicates that it
should only be used for debugging) we have to do a bit of math for the
other parents: target_freq * divider = rate of parent clock
Bit 8 above is the enable bit, so we can ignore it here. Bits 11:9 are
the mux index and bits 6:0 are the 0-based divider (so we need to add
1). This gives us:
- mux 0 (160MHz * 4) = fclk_div4 (actual rate = 637.5MHz, off by 2.5MHz)
- mux 1 (212MHz * 4) = fclk_div3 (actual rate = 850MHz, off by 2MHz)
- mux 2 (255MHz * 2) = fclk_div5 (matches exactly 510MHz)
- mux 3 (182MHz * 2) = fclk_div7 (actual rate = 346.3MHz, off by 0.3MHz)

[0] https://github.com/khadas/linux/blob/9587681285cb/drivers/amlogic/amlnf/dev/amlnf_ctrl.c#L314

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>