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1 // SPDX-License-Identifier: GPL-2.0-only

2 /*

3 * NAU88L24 ALSA SoC audio driver

4 *

6 * Author: John Hsu <KCHSU0@nuvoton.com>

7 */

8

9 #include <linux/module.h>

10 #include <linux/delay.h>

11 #include <linux/dmi.h>

12 #include <linux/init.h>

13 #include <linux/i2c.h>

14 #include <linux/regmap.h>

15 #include <linux/slab.h>

16 #include <linux/clk.h>

17 #include <linux/acpi.h>

18 #include <linux/math64.h>

19 #include <linux/semaphore.h>

20

21 #include <sound/initval.h>

22 #include <sound/tlv.h>

23 #include <sound/core.h>

24 #include <sound/pcm.h>

25 #include <sound/pcm_params.h>

26 #include <sound/soc.h>

27 #include <sound/jack.h>

28

29 #include "nau8824.h"

30

31 #define NAU8824_JD_ACTIVE_HIGH BIT(0)

32

33 static int nau8824_quirk;

34 static int quirk_override = -1;

35 module_param_named(quirk, quirk_override, uint, 0444);

36 MODULE_PARM_DESC(quirk, "Board-specific quirk override");

37

38 static int nau8824_config_sysclk(struct nau8824 *nau8824,

39 int clk_id, unsigned int freq);

40 static bool nau8824_is_jack_inserted(struct nau8824 *nau8824);

41

42 /* the ADC threshold of headset */

43 #define DMIC_CLK 3072000

44

45 /* the ADC threshold of headset */

46 #define HEADSET_SARADC_THD 0x80

47

48 /* the parameter threshold of FLL */

49 #define NAU_FREF_MAX 13500000

50 #define NAU_FVCO_MAX 100000000

51 #define NAU_FVCO_MIN 90000000

52

53 /* scaling for mclk from sysclk_src output */

54 static const struct nau8824_fll_attr mclk_src_scaling[] = {

55 { 1, 0x0 },

56 { 2, 0x2 },

57 { 4, 0x3 },

58 { 8, 0x4 },

59 { 16, 0x5 },

60 { 32, 0x6 },

61 { 3, 0x7 },

62 { 6, 0xa },

63 { 12, 0xb },

64 { 24, 0xc },

65 };

66

67 /* ratio for input clk freq */

68 static const struct nau8824_fll_attr fll_ratio[] = {

69 { 512000, 0x01 },

70 { 256000, 0x02 },

71 { 128000, 0x04 },

72 { 64000, 0x08 },

73 { 32000, 0x10 },

74 { 8000, 0x20 },

75 { 4000, 0x40 },

76 };

77

78 static const struct nau8824_fll_attr fll_pre_scalar[] = {

79 { 1, 0x0 },

80 { 2, 0x1 },

81 { 4, 0x2 },

82 { 8, 0x3 },

83 };

84

85 /* the maximum frequency of CLK_ADC and CLK_DAC */

86 #define CLK_DA_AD_MAX 6144000

87

88 /* over sampling rate */

89 static const struct nau8824_osr_attr osr_dac_sel[] = {

90 { 64, 2 }, /* OSR 64, SRC 1/4 */

91 { 256, 0 }, /* OSR 256, SRC 1 */

92 { 128, 1 }, /* OSR 128, SRC 1/2 */

93 { 0, 0 },

94 { 32, 3 }, /* OSR 32, SRC 1/8 */

95 };

96

97 static const struct nau8824_osr_attr osr_adc_sel[] = {

98 { 32, 3 }, /* OSR 32, SRC 1/8 */

99 { 64, 2 }, /* OSR 64, SRC 1/4 */

100 { 128, 1 }, /* OSR 128, SRC 1/2 */

101 { 256, 0 }, /* OSR 256, SRC 1 */

102 };

103

104 static const struct reg_default nau8824_reg_defaults[] = {

105 { NAU8824_REG_ENA_CTRL, 0x0000 },

106 { NAU8824_REG_CLK_GATING_ENA, 0x0000 },

107 { NAU8824_REG_CLK_DIVIDER, 0x0000 },

108 { NAU8824_REG_FLL1, 0x0000 },

109 { NAU8824_REG_FLL2, 0x3126 },

110 { NAU8824_REG_FLL3, 0x0008 },

111 { NAU8824_REG_FLL4, 0x0010 },

112 { NAU8824_REG_FLL5, 0xC000 },

113 { NAU8824_REG_FLL6, 0x6000 },

114 { NAU8824_REG_FLL_VCO_RSV, 0xF13C },

115 { NAU8824_REG_JACK_DET_CTRL, 0x0000 },

116 { NAU8824_REG_INTERRUPT_SETTING_1, 0x0000 },

117 { NAU8824_REG_IRQ, 0x0000 },

118 { NAU8824_REG_CLEAR_INT_REG, 0x0000 },

119 { NAU8824_REG_INTERRUPT_SETTING, 0x1000 },

120 { NAU8824_REG_SAR_ADC, 0x0015 },

121 { NAU8824_REG_VDET_COEFFICIENT, 0x0110 },

122 { NAU8824_REG_VDET_THRESHOLD_1, 0x0000 },

123 { NAU8824_REG_VDET_THRESHOLD_2, 0x0000 },

124 { NAU8824_REG_VDET_THRESHOLD_3, 0x0000 },

125 { NAU8824_REG_VDET_THRESHOLD_4, 0x0000 },

126 { NAU8824_REG_GPIO_SEL, 0x0000 },

127 { NAU8824_REG_PORT0_I2S_PCM_CTRL_1, 0x000B },

128 { NAU8824_REG_PORT0_I2S_PCM_CTRL_2, 0x0010 },

129 { NAU8824_REG_PORT0_LEFT_TIME_SLOT, 0x0000 },

130 { NAU8824_REG_PORT0_RIGHT_TIME_SLOT, 0x0000 },

131 { NAU8824_REG_TDM_CTRL, 0x0000 },

132 { NAU8824_REG_ADC_HPF_FILTER, 0x0000 },

133 { NAU8824_REG_ADC_FILTER_CTRL, 0x0002 },

134 { NAU8824_REG_DAC_FILTER_CTRL_1, 0x0000 },

135 { NAU8824_REG_DAC_FILTER_CTRL_2, 0x0000 },

136 { NAU8824_REG_NOTCH_FILTER_1, 0x0000 },

137 { NAU8824_REG_NOTCH_FILTER_2, 0x0000 },

138 { NAU8824_REG_EQ1_LOW, 0x112C },

139 { NAU8824_REG_EQ2_EQ3, 0x2C2C },

140 { NAU8824_REG_EQ4_EQ5, 0x2C2C },

141 { NAU8824_REG_ADC_CH0_DGAIN_CTRL, 0x0100 },

142 { NAU8824_REG_ADC_CH1_DGAIN_CTRL, 0x0100 },

143 { NAU8824_REG_ADC_CH2_DGAIN_CTRL, 0x0100 },

144 { NAU8824_REG_ADC_CH3_DGAIN_CTRL, 0x0100 },

145 { NAU8824_REG_DAC_MUTE_CTRL, 0x0000 },

146 { NAU8824_REG_DAC_CH0_DGAIN_CTRL, 0x0100 },

147 { NAU8824_REG_DAC_CH1_DGAIN_CTRL, 0x0100 },

148 { NAU8824_REG_ADC_TO_DAC_ST, 0x0000 },

149 { NAU8824_REG_DRC_KNEE_IP12_ADC_CH01, 0x1486 },

150 { NAU8824_REG_DRC_KNEE_IP34_ADC_CH01, 0x0F12 },

151 { NAU8824_REG_DRC_SLOPE_ADC_CH01, 0x25FF },

152 { NAU8824_REG_DRC_ATKDCY_ADC_CH01, 0x3457 },

153 { NAU8824_REG_DRC_KNEE_IP12_ADC_CH23, 0x1486 },

154 { NAU8824_REG_DRC_KNEE_IP34_ADC_CH23, 0x0F12 },

155 { NAU8824_REG_DRC_SLOPE_ADC_CH23, 0x25FF },

156 { NAU8824_REG_DRC_ATKDCY_ADC_CH23, 0x3457 },

157 { NAU8824_REG_DRC_GAINL_ADC0, 0x0200 },

158 { NAU8824_REG_DRC_GAINL_ADC1, 0x0200 },

159 { NAU8824_REG_DRC_GAINL_ADC2, 0x0200 },

160 { NAU8824_REG_DRC_GAINL_ADC3, 0x0200 },

161 { NAU8824_REG_DRC_KNEE_IP12_DAC, 0x1486 },

162 { NAU8824_REG_DRC_KNEE_IP34_DAC, 0x0F12 },

163 { NAU8824_REG_DRC_SLOPE_DAC, 0x25F9 },

164 { NAU8824_REG_DRC_ATKDCY_DAC, 0x3457 },

165 { NAU8824_REG_DRC_GAIN_DAC_CH0, 0x0200 },

166 { NAU8824_REG_DRC_GAIN_DAC_CH1, 0x0200 },

167 { NAU8824_REG_MODE, 0x0000 },

168 { NAU8824_REG_MODE1, 0x0000 },

169 { NAU8824_REG_MODE2, 0x0000 },

170 { NAU8824_REG_CLASSG, 0x0000 },

171 { NAU8824_REG_OTP_EFUSE, 0x0000 },

172 { NAU8824_REG_OTPDOUT_1, 0x0000 },

173 { NAU8824_REG_OTPDOUT_2, 0x0000 },

174 { NAU8824_REG_MISC_CTRL, 0x0000 },

175 { NAU8824_REG_I2C_TIMEOUT, 0xEFFF },

176 { NAU8824_REG_TEST_MODE, 0x0000 },

177 { NAU8824_REG_I2C_DEVICE_ID, 0x1AF1 },

178 { NAU8824_REG_SAR_ADC_DATA_OUT, 0x00FF },

179 { NAU8824_REG_BIAS_ADJ, 0x0000 },

180 { NAU8824_REG_PGA_GAIN, 0x0000 },

181 { NAU8824_REG_TRIM_SETTINGS, 0x0000 },

182 { NAU8824_REG_ANALOG_CONTROL_1, 0x0000 },

183 { NAU8824_REG_ANALOG_CONTROL_2, 0x0000 },

184 { NAU8824_REG_ENABLE_LO, 0x0000 },

185 { NAU8824_REG_GAIN_LO, 0x0000 },

186 { NAU8824_REG_CLASSD_GAIN_1, 0x0000 },

187 { NAU8824_REG_CLASSD_GAIN_2, 0x0000 },

188 { NAU8824_REG_ANALOG_ADC_1, 0x0011 },

189 { NAU8824_REG_ANALOG_ADC_2, 0x0020 },

190 { NAU8824_REG_RDAC, 0x0008 },

191 { NAU8824_REG_MIC_BIAS, 0x0006 },

192 { NAU8824_REG_HS_VOLUME_CONTROL, 0x0000 },

193 { NAU8824_REG_BOOST, 0x0000 },

194 { NAU8824_REG_FEPGA, 0x0000 },

195 { NAU8824_REG_FEPGA_II, 0x0000 },

196 { NAU8824_REG_FEPGA_SE, 0x0000 },

197 { NAU8824_REG_FEPGA_ATTENUATION, 0x0000 },

198 { NAU8824_REG_ATT_PORT0, 0x0000 },

199 { NAU8824_REG_ATT_PORT1, 0x0000 },

200 { NAU8824_REG_POWER_UP_CONTROL, 0x0000 },

201 { NAU8824_REG_CHARGE_PUMP_CONTROL, 0x0300 },

202 { NAU8824_REG_CHARGE_PUMP_INPUT, 0x0013 },

203 };

204

205 static int nau8824_sema_acquire(struct nau8824 *nau8824, long timeout)

206 {

207 int ret;

208

209 if (timeout) {

210 ret = down_timeout(&nau8824->jd_sem, timeout);

211 if (ret < 0)

212 dev_warn(nau8824->dev, "Acquire semaphore timeout\n");

213 } else {

214 ret = down_interruptible(&nau8824->jd_sem);

215 if (ret < 0)

216 dev_warn(nau8824->dev, "Acquire semaphore fail\n");

217 }

218

219 return ret;

220 }

221

222 static inline void nau8824_sema_release(struct nau8824 *nau8824)

223 {

224 up(&nau8824->jd_sem);

225 }

226

227 static bool nau8824_readable_reg(struct device *dev, unsigned int reg)

228 {

229 switch (reg) {

230 case NAU8824_REG_ENA_CTRL ... NAU8824_REG_FLL_VCO_RSV:

231 case NAU8824_REG_JACK_DET_CTRL:

232 case NAU8824_REG_INTERRUPT_SETTING_1:

233 case NAU8824_REG_IRQ:

234 case NAU8824_REG_CLEAR_INT_REG ... NAU8824_REG_VDET_THRESHOLD_4:

235 case NAU8824_REG_GPIO_SEL:

236 case NAU8824_REG_PORT0_I2S_PCM_CTRL_1 ... NAU8824_REG_TDM_CTRL:

237 case NAU8824_REG_ADC_HPF_FILTER ... NAU8824_REG_EQ4_EQ5:

238 case NAU8824_REG_ADC_CH0_DGAIN_CTRL ... NAU8824_REG_ADC_TO_DAC_ST:

239 case NAU8824_REG_DRC_KNEE_IP12_ADC_CH01 ... NAU8824_REG_DRC_GAINL_ADC3:

240 case NAU8824_REG_DRC_KNEE_IP12_DAC ... NAU8824_REG_DRC_GAIN_DAC_CH1:

241 case NAU8824_REG_CLASSG ... NAU8824_REG_OTP_EFUSE:

242 case NAU8824_REG_OTPDOUT_1 ... NAU8824_REG_OTPDOUT_2:

243 case NAU8824_REG_I2C_TIMEOUT:

244 case NAU8824_REG_I2C_DEVICE_ID ... NAU8824_REG_SAR_ADC_DATA_OUT:

245 case NAU8824_REG_BIAS_ADJ ... NAU8824_REG_CLASSD_GAIN_2:

246 case NAU8824_REG_ANALOG_ADC_1 ... NAU8824_REG_ATT_PORT1:

247 case NAU8824_REG_POWER_UP_CONTROL ... NAU8824_REG_CHARGE_PUMP_INPUT:

248 return true;

249 default:

250 return false;

251 }

252

253 }

254

255 static bool nau8824_writeable_reg(struct device *dev, unsigned int reg)

256 {

257 switch (reg) {

258 case NAU8824_REG_RESET ... NAU8824_REG_FLL_VCO_RSV:

259 case NAU8824_REG_JACK_DET_CTRL:

260 case NAU8824_REG_INTERRUPT_SETTING_1:

261 case NAU8824_REG_CLEAR_INT_REG ... NAU8824_REG_VDET_THRESHOLD_4:

262 case NAU8824_REG_GPIO_SEL:

263 case NAU8824_REG_PORT0_I2S_PCM_CTRL_1 ... NAU8824_REG_TDM_CTRL:

264 case NAU8824_REG_ADC_HPF_FILTER ... NAU8824_REG_EQ4_EQ5:

265 case NAU8824_REG_ADC_CH0_DGAIN_CTRL ... NAU8824_REG_ADC_TO_DAC_ST:

266 case NAU8824_REG_DRC_KNEE_IP12_ADC_CH01:

267 case NAU8824_REG_DRC_KNEE_IP34_ADC_CH01:

268 case NAU8824_REG_DRC_SLOPE_ADC_CH01:

269 case NAU8824_REG_DRC_ATKDCY_ADC_CH01:

270 case NAU8824_REG_DRC_KNEE_IP12_ADC_CH23:

271 case NAU8824_REG_DRC_KNEE_IP34_ADC_CH23:

272 case NAU8824_REG_DRC_SLOPE_ADC_CH23:

273 case NAU8824_REG_DRC_ATKDCY_ADC_CH23:

274 case NAU8824_REG_DRC_KNEE_IP12_DAC ... NAU8824_REG_DRC_ATKDCY_DAC:

275 case NAU8824_REG_CLASSG ... NAU8824_REG_OTP_EFUSE:

276 case NAU8824_REG_I2C_TIMEOUT:

277 case NAU8824_REG_BIAS_ADJ ... NAU8824_REG_CLASSD_GAIN_2:

278 case NAU8824_REG_ANALOG_ADC_1 ... NAU8824_REG_ATT_PORT1:

279 case NAU8824_REG_POWER_UP_CONTROL ... NAU8824_REG_CHARGE_PUMP_CONTROL:

280 return true;

281 default:

282 return false;

283 }

284 }

285

286 static bool nau8824_volatile_reg(struct device *dev, unsigned int reg)

287 {

288 switch (reg) {

289 case NAU8824_REG_RESET:

290 case NAU8824_REG_IRQ ... NAU8824_REG_CLEAR_INT_REG:

291 case NAU8824_REG_DRC_GAINL_ADC0 ... NAU8824_REG_DRC_GAINL_ADC3:

292 case NAU8824_REG_DRC_GAIN_DAC_CH0 ... NAU8824_REG_DRC_GAIN_DAC_CH1:

293 case NAU8824_REG_OTPDOUT_1 ... NAU8824_REG_OTPDOUT_2:

294 case NAU8824_REG_I2C_DEVICE_ID ... NAU8824_REG_SAR_ADC_DATA_OUT:

295 case NAU8824_REG_CHARGE_PUMP_INPUT:

296 return true;

297 default:

298 return false;

299 }

300 }

301

302 static const char * const nau8824_companding[] = {

303 "Off", "NC", "u-law", "A-law" };

304

305 static const struct soc_enum nau8824_companding_adc_enum =

306 SOC_ENUM_SINGLE(NAU8824_REG_PORT0_I2S_PCM_CTRL_1, 12,

307 ARRAY_SIZE(nau8824_companding), nau8824_companding);

308

309 static const struct soc_enum nau8824_companding_dac_enum =

310 SOC_ENUM_SINGLE(NAU8824_REG_PORT0_I2S_PCM_CTRL_1, 14,

311 ARRAY_SIZE(nau8824_companding), nau8824_companding);

312

313 static const char * const nau8824_adc_decimation[] = {

314 "32", "64", "128", "256" };

315

316 static const struct soc_enum nau8824_adc_decimation_enum =

317 SOC_ENUM_SINGLE(NAU8824_REG_ADC_FILTER_CTRL, 0,

318 ARRAY_SIZE(nau8824_adc_decimation), nau8824_adc_decimation);

319

320 static const char * const nau8824_dac_oversampl[] = {

321 "64", "256", "128", "", "32" };

322

323 static const struct soc_enum nau8824_dac_oversampl_enum =

324 SOC_ENUM_SINGLE(NAU8824_REG_DAC_FILTER_CTRL_1, 0,

325 ARRAY_SIZE(nau8824_dac_oversampl), nau8824_dac_oversampl);

326

327 static const char * const nau8824_input_channel[] = {

328 "Input CH0", "Input CH1", "Input CH2", "Input CH3" };

329

330 static const struct soc_enum nau8824_adc_ch0_enum =

331 SOC_ENUM_SINGLE(NAU8824_REG_ADC_CH0_DGAIN_CTRL, 9,

332 ARRAY_SIZE(nau8824_input_channel), nau8824_input_channel);

333

334 static const struct soc_enum nau8824_adc_ch1_enum =

335 SOC_ENUM_SINGLE(NAU8824_REG_ADC_CH1_DGAIN_CTRL, 9,

336 ARRAY_SIZE(nau8824_input_channel), nau8824_input_channel);

337

338 static const struct soc_enum nau8824_adc_ch2_enum =

339 SOC_ENUM_SINGLE(NAU8824_REG_ADC_CH2_DGAIN_CTRL, 9,

340 ARRAY_SIZE(nau8824_input_channel), nau8824_input_channel);

341

342 static const struct soc_enum nau8824_adc_ch3_enum =

343 SOC_ENUM_SINGLE(NAU8824_REG_ADC_CH3_DGAIN_CTRL, 9,

344 ARRAY_SIZE(nau8824_input_channel), nau8824_input_channel);

345

346 static const char * const nau8824_tdm_slot[] = {

347 "Slot 0", "Slot 1", "Slot 2", "Slot 3" };

348

349 static const struct soc_enum nau8824_dac_left_sel_enum =

350 SOC_ENUM_SINGLE(NAU8824_REG_TDM_CTRL, 6,

351 ARRAY_SIZE(nau8824_tdm_slot), nau8824_tdm_slot);

352

353 static const struct soc_enum nau8824_dac_right_sel_enum =

354 SOC_ENUM_SINGLE(NAU8824_REG_TDM_CTRL, 4,

355 ARRAY_SIZE(nau8824_tdm_slot), nau8824_tdm_slot);

356

357 static const DECLARE_TLV_DB_MINMAX_MUTE(spk_vol_tlv, 0, 2400);

358 static const DECLARE_TLV_DB_MINMAX(hp_vol_tlv, -3000, 0);

359 static const DECLARE_TLV_DB_SCALE(mic_vol_tlv, 0, 200, 0);

360 static const DECLARE_TLV_DB_SCALE(dmic_vol_tlv, -12800, 50, 0);

361

362 static const struct snd_kcontrol_new nau8824_snd_controls[] = {

363 SOC_ENUM("ADC Companding", nau8824_companding_adc_enum),

364 SOC_ENUM("DAC Companding", nau8824_companding_dac_enum),

365

366 SOC_ENUM("ADC Decimation Rate", nau8824_adc_decimation_enum),

367 SOC_ENUM("DAC Oversampling Rate", nau8824_dac_oversampl_enum),

368

369 SOC_SINGLE_TLV("Speaker Right DACR Volume",

370 NAU8824_REG_CLASSD_GAIN_1, 8, 0x1f, 0, spk_vol_tlv),

371 SOC_SINGLE_TLV("Speaker Left DACL Volume",

372 NAU8824_REG_CLASSD_GAIN_2, 0, 0x1f, 0, spk_vol_tlv),

373 SOC_SINGLE_TLV("Speaker Left DACR Volume",

374 NAU8824_REG_CLASSD_GAIN_1, 0, 0x1f, 0, spk_vol_tlv),

375 SOC_SINGLE_TLV("Speaker Right DACL Volume",

376 NAU8824_REG_CLASSD_GAIN_2, 8, 0x1f, 0, spk_vol_tlv),

377

378 SOC_SINGLE_TLV("Headphone Right DACR Volume",

379 NAU8824_REG_ATT_PORT0, 8, 0x1f, 0, hp_vol_tlv),

380 SOC_SINGLE_TLV("Headphone Left DACL Volume",

381 NAU8824_REG_ATT_PORT0, 0, 0x1f, 0, hp_vol_tlv),

382 SOC_SINGLE_TLV("Headphone Right DACL Volume",

383 NAU8824_REG_ATT_PORT1, 8, 0x1f, 0, hp_vol_tlv),

384 SOC_SINGLE_TLV("Headphone Left DACR Volume",

385 NAU8824_REG_ATT_PORT1, 0, 0x1f, 0, hp_vol_tlv),

386

387 SOC_SINGLE_TLV("MIC1 Volume", NAU8824_REG_FEPGA_II,

388 NAU8824_FEPGA_GAINL_SFT, 0x12, 0, mic_vol_tlv),

389 SOC_SINGLE_TLV("MIC2 Volume", NAU8824_REG_FEPGA_II,

390 NAU8824_FEPGA_GAINR_SFT, 0x12, 0, mic_vol_tlv),

391

392 SOC_SINGLE_TLV("DMIC1 Volume", NAU8824_REG_ADC_CH0_DGAIN_CTRL,

393 0, 0x164, 0, dmic_vol_tlv),

394 SOC_SINGLE_TLV("DMIC2 Volume", NAU8824_REG_ADC_CH1_DGAIN_CTRL,

395 0, 0x164, 0, dmic_vol_tlv),

396 SOC_SINGLE_TLV("DMIC3 Volume", NAU8824_REG_ADC_CH2_DGAIN_CTRL,

397 0, 0x164, 0, dmic_vol_tlv),

398 SOC_SINGLE_TLV("DMIC4 Volume", NAU8824_REG_ADC_CH3_DGAIN_CTRL,

399 0, 0x164, 0, dmic_vol_tlv),

400

401 SOC_ENUM("ADC CH0 Select", nau8824_adc_ch0_enum),

402 SOC_ENUM("ADC CH1 Select", nau8824_adc_ch1_enum),

403 SOC_ENUM("ADC CH2 Select", nau8824_adc_ch2_enum),

404 SOC_ENUM("ADC CH3 Select", nau8824_adc_ch3_enum),

405

406 SOC_SINGLE("ADC CH0 TX Switch", NAU8824_REG_TDM_CTRL, 0, 1, 0),

407 SOC_SINGLE("ADC CH1 TX Switch", NAU8824_REG_TDM_CTRL, 1, 1, 0),

408 SOC_SINGLE("ADC CH2 TX Switch", NAU8824_REG_TDM_CTRL, 2, 1, 0),

409 SOC_SINGLE("ADC CH3 TX Switch", NAU8824_REG_TDM_CTRL, 3, 1, 0),

410

411 SOC_ENUM("DACL Channel Source", nau8824_dac_left_sel_enum),

412 SOC_ENUM("DACR Channel Source", nau8824_dac_right_sel_enum),

413

414 SOC_SINGLE("DACL LR Mix", NAU8824_REG_DAC_MUTE_CTRL, 0, 1, 0),

415 SOC_SINGLE("DACR LR Mix", NAU8824_REG_DAC_MUTE_CTRL, 1, 1, 0),

416

417 SOC_SINGLE("THD for key media",

418 NAU8824_REG_VDET_THRESHOLD_1, 8, 0xff, 0),

419 SOC_SINGLE("THD for key voice command",

420 NAU8824_REG_VDET_THRESHOLD_1, 0, 0xff, 0),

421 SOC_SINGLE("THD for key volume up",

422 NAU8824_REG_VDET_THRESHOLD_2, 8, 0xff, 0),

423 SOC_SINGLE("THD for key volume down",

424 NAU8824_REG_VDET_THRESHOLD_2, 0, 0xff, 0),

425 };

426

427 static int nau8824_output_dac_event(struct snd_soc_dapm_widget *w,

428 struct snd_kcontrol *kcontrol, int event)

429 {

430 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);

431 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);

432

433 switch (event) {

434 case SND_SOC_DAPM_PRE_PMU:

435 /* Disables the TESTDAC to let DAC signal pass through. */

436 regmap_update_bits(nau8824->regmap, NAU8824_REG_ENABLE_LO,

437 NAU8824_TEST_DAC_EN, 0);

438 break;

439 case SND_SOC_DAPM_POST_PMD:

440 regmap_update_bits(nau8824->regmap, NAU8824_REG_ENABLE_LO,

441 NAU8824_TEST_DAC_EN, NAU8824_TEST_DAC_EN);

442 break;

443 default:

444 return -EINVAL;

445 }

446

447 return 0;

448 }

449

450 static int nau8824_spk_event(struct snd_soc_dapm_widget *w,

451 struct snd_kcontrol *kcontrol, int event)

452 {

453 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);

454 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);

455

456 switch (event) {

457 case SND_SOC_DAPM_PRE_PMU:

458 regmap_update_bits(nau8824->regmap,

459 NAU8824_REG_ANALOG_CONTROL_2,

460 NAU8824_CLASSD_CLAMP_DIS, NAU8824_CLASSD_CLAMP_DIS);

461 break;

462 case SND_SOC_DAPM_POST_PMD:

463 regmap_update_bits(nau8824->regmap,

464 NAU8824_REG_ANALOG_CONTROL_2,

465 NAU8824_CLASSD_CLAMP_DIS, 0);

466 break;

467 default:

468 return -EINVAL;

469 }

470

471 return 0;

472 }

473

474 static int nau8824_pump_event(struct snd_soc_dapm_widget *w,

475 struct snd_kcontrol *kcontrol, int event)

476 {

477 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);

478 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);

479

480 switch (event) {

481 case SND_SOC_DAPM_POST_PMU:

482 /* Prevent startup click by letting charge pump to ramp up */

483 msleep(10);

484 regmap_update_bits(nau8824->regmap,

485 NAU8824_REG_CHARGE_PUMP_CONTROL,

486 NAU8824_JAMNODCLOW, NAU8824_JAMNODCLOW);

487 break;

488 case SND_SOC_DAPM_PRE_PMD:

489 regmap_update_bits(nau8824->regmap,

490 NAU8824_REG_CHARGE_PUMP_CONTROL,

491 NAU8824_JAMNODCLOW, 0);

492 break;

493 default:

494 return -EINVAL;

495 }

496

497 return 0;

498 }

499

500 static int system_clock_control(struct snd_soc_dapm_widget *w,

501 struct snd_kcontrol *k, int event)

502 {

503 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);

504 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);

505 struct regmap *regmap = nau8824->regmap;

506 unsigned int value;

507 bool clk_fll, error;

508

509 if (SND_SOC_DAPM_EVENT_OFF(event)) {

510 dev_dbg(nau8824->dev, "system clock control : POWER OFF\n");

511 /* Set clock source to disable or internal clock before the

512 * playback or capture end. Codec needs clock for Jack

513 * detection and button press if jack inserted; otherwise,

514 * the clock should be closed.

515 */

516 if (nau8824_is_jack_inserted(nau8824)) {

517 nau8824_config_sysclk(nau8824,

518 NAU8824_CLK_INTERNAL, 0);

519 } else {

520 nau8824_config_sysclk(nau8824, NAU8824_CLK_DIS, 0);

521 }

522 } else {

523 dev_dbg(nau8824->dev, "system clock control : POWER ON\n");

524 /* Check the clock source setting is proper or not

525 * no matter the source is from FLL or MCLK.

526 */

527 regmap_read(regmap, NAU8824_REG_FLL1, &value);

528 clk_fll = value & NAU8824_FLL_RATIO_MASK;

529 /* It's error to use internal clock when playback */

530 regmap_read(regmap, NAU8824_REG_FLL6, &value);

531 error = value & NAU8824_DCO_EN;

532 if (!error) {

533 /* Check error depending on source is FLL or MCLK. */

534 regmap_read(regmap, NAU8824_REG_CLK_DIVIDER, &value);

535 if (clk_fll)

536 error = !(value & NAU8824_CLK_SRC_VCO);

537 else

538 error = value & NAU8824_CLK_SRC_VCO;

539 }

540 /* Recover the clock source setting if error. */

541 if (error) {

542 if (clk_fll) {

543 regmap_update_bits(regmap,

544 NAU8824_REG_FLL6, NAU8824_DCO_EN, 0);

545 regmap_update_bits(regmap,

546 NAU8824_REG_CLK_DIVIDER,

547 NAU8824_CLK_SRC_MASK,

548 NAU8824_CLK_SRC_VCO);

549 } else {

550 nau8824_config_sysclk(nau8824,

551 NAU8824_CLK_MCLK, 0);

552 }

553 }

554 }

555

556 return 0;

557 }

558

559 static int dmic_clock_control(struct snd_soc_dapm_widget *w,

560 struct snd_kcontrol *k, int event)

561 {

562 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);

563 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);

564 int src;

565

566 /* The DMIC clock is gotten from system clock (256fs) divided by

567 * DMIC_SRC (1, 2, 4, 8, 16, 32). The clock has to be equal or

568 * less than 3.072 MHz.

569 */

570 for (src = 0; src < 5; src++) {

571 if ((0x1 << (8 - src)) * nau8824->fs <= DMIC_CLK)

572 break;

573 }

574 dev_dbg(nau8824->dev, "dmic src %d for mclk %d\n", src, nau8824->fs * 256);

575 regmap_update_bits(nau8824->regmap, NAU8824_REG_CLK_DIVIDER,

576 NAU8824_CLK_DMIC_SRC_MASK, (src << NAU8824_CLK_DMIC_SRC_SFT));

577

578 return 0;

579 }

580

581 static const struct snd_kcontrol_new nau8824_adc_ch0_dmic =

582 SOC_DAPM_SINGLE("Switch", NAU8824_REG_ENA_CTRL,

583 NAU8824_ADC_CH0_DMIC_SFT, 1, 0);

584

585 static const struct snd_kcontrol_new nau8824_adc_ch1_dmic =

586 SOC_DAPM_SINGLE("Switch", NAU8824_REG_ENA_CTRL,

587 NAU8824_ADC_CH1_DMIC_SFT, 1, 0);

588

589 static const struct snd_kcontrol_new nau8824_adc_ch2_dmic =

590 SOC_DAPM_SINGLE("Switch", NAU8824_REG_ENA_CTRL,

591 NAU8824_ADC_CH2_DMIC_SFT, 1, 0);

592

593 static const struct snd_kcontrol_new nau8824_adc_ch3_dmic =

594 SOC_DAPM_SINGLE("Switch", NAU8824_REG_ENA_CTRL,

595 NAU8824_ADC_CH3_DMIC_SFT, 1, 0);

596

597 static const struct snd_kcontrol_new nau8824_adc_left_mixer[] = {

598 SOC_DAPM_SINGLE("MIC Switch", NAU8824_REG_FEPGA,

599 NAU8824_FEPGA_MODEL_MIC1_SFT, 1, 0),

600 SOC_DAPM_SINGLE("HSMIC Switch", NAU8824_REG_FEPGA,

601 NAU8824_FEPGA_MODEL_HSMIC_SFT, 1, 0),

602 };

603

604 static const struct snd_kcontrol_new nau8824_adc_right_mixer[] = {

605 SOC_DAPM_SINGLE("MIC Switch", NAU8824_REG_FEPGA,

606 NAU8824_FEPGA_MODER_MIC2_SFT, 1, 0),

607 SOC_DAPM_SINGLE("HSMIC Switch", NAU8824_REG_FEPGA,

608 NAU8824_FEPGA_MODER_HSMIC_SFT, 1, 0),

609 };

610

611 static const struct snd_kcontrol_new nau8824_hp_left_mixer[] = {

612 SOC_DAPM_SINGLE("DAC Right Switch", NAU8824_REG_ENABLE_LO,

613 NAU8824_DACR_HPL_EN_SFT, 1, 0),

614 SOC_DAPM_SINGLE("DAC Left Switch", NAU8824_REG_ENABLE_LO,

615 NAU8824_DACL_HPL_EN_SFT, 1, 0),

616 };

617

618 static const struct snd_kcontrol_new nau8824_hp_right_mixer[] = {

619 SOC_DAPM_SINGLE("DAC Left Switch", NAU8824_REG_ENABLE_LO,

620 NAU8824_DACL_HPR_EN_SFT, 1, 0),

621 SOC_DAPM_SINGLE("DAC Right Switch", NAU8824_REG_ENABLE_LO,

622 NAU8824_DACR_HPR_EN_SFT, 1, 0),

623 };

624

625 static const char * const nau8824_dac_src[] = { "DACL", "DACR" };

626

627 static SOC_ENUM_SINGLE_DECL(

628 nau8824_dacl_enum, NAU8824_REG_DAC_CH0_DGAIN_CTRL,

629 NAU8824_DAC_CH0_SEL_SFT, nau8824_dac_src);

630

631 static SOC_ENUM_SINGLE_DECL(

632 nau8824_dacr_enum, NAU8824_REG_DAC_CH1_DGAIN_CTRL,

633 NAU8824_DAC_CH1_SEL_SFT, nau8824_dac_src);

634

635 static const struct snd_kcontrol_new nau8824_dacl_mux =

636 SOC_DAPM_ENUM("DACL Source", nau8824_dacl_enum);

637

638 static const struct snd_kcontrol_new nau8824_dacr_mux =

639 SOC_DAPM_ENUM("DACR Source", nau8824_dacr_enum);

640

641

642 static const struct snd_soc_dapm_widget nau8824_dapm_widgets[] = {

643 SND_SOC_DAPM_SUPPLY("System Clock", SND_SOC_NOPM, 0, 0,

644 system_clock_control, SND_SOC_DAPM_POST_PMD |

645 SND_SOC_DAPM_POST_PMU),

646

647 SND_SOC_DAPM_INPUT("HSMIC1"),

648 SND_SOC_DAPM_INPUT("HSMIC2"),

649 SND_SOC_DAPM_INPUT("MIC1"),

650 SND_SOC_DAPM_INPUT("MIC2"),

651 SND_SOC_DAPM_INPUT("DMIC1"),

652 SND_SOC_DAPM_INPUT("DMIC2"),

653 SND_SOC_DAPM_INPUT("DMIC3"),

654 SND_SOC_DAPM_INPUT("DMIC4"),

655

656 SND_SOC_DAPM_SUPPLY("SAR", NAU8824_REG_SAR_ADC,

657 NAU8824_SAR_ADC_EN_SFT, 0, NULL, 0),

658 SND_SOC_DAPM_SUPPLY("MICBIAS", NAU8824_REG_MIC_BIAS,

659 NAU8824_MICBIAS_POWERUP_SFT, 0, NULL, 0),

660 SND_SOC_DAPM_SUPPLY("DMIC12 Power", NAU8824_REG_BIAS_ADJ,

661 NAU8824_DMIC1_EN_SFT, 0, NULL, 0),

662 SND_SOC_DAPM_SUPPLY("DMIC34 Power", NAU8824_REG_BIAS_ADJ,

663 NAU8824_DMIC2_EN_SFT, 0, NULL, 0),

664 SND_SOC_DAPM_SUPPLY("DMIC Clock", SND_SOC_NOPM, 0, 0,

665 dmic_clock_control, SND_SOC_DAPM_POST_PMU),

666

667 SND_SOC_DAPM_SWITCH("DMIC1 Enable", SND_SOC_NOPM,

668 0, 0, &nau8824_adc_ch0_dmic),

669 SND_SOC_DAPM_SWITCH("DMIC2 Enable", SND_SOC_NOPM,

670 0, 0, &nau8824_adc_ch1_dmic),

671 SND_SOC_DAPM_SWITCH("DMIC3 Enable", SND_SOC_NOPM,

672 0, 0, &nau8824_adc_ch2_dmic),

673 SND_SOC_DAPM_SWITCH("DMIC4 Enable", SND_SOC_NOPM,

674 0, 0, &nau8824_adc_ch3_dmic),

675

676 SND_SOC_DAPM_MIXER("Left ADC", NAU8824_REG_POWER_UP_CONTROL,

677 12, 0, nau8824_adc_left_mixer,

678 ARRAY_SIZE(nau8824_adc_left_mixer)),

679 SND_SOC_DAPM_MIXER("Right ADC", NAU8824_REG_POWER_UP_CONTROL,

680 13, 0, nau8824_adc_right_mixer,

681 ARRAY_SIZE(nau8824_adc_right_mixer)),

682

683 SND_SOC_DAPM_ADC("ADCL", NULL, NAU8824_REG_ANALOG_ADC_2,

684 NAU8824_ADCL_EN_SFT, 0),

685 SND_SOC_DAPM_ADC("ADCR", NULL, NAU8824_REG_ANALOG_ADC_2,

686 NAU8824_ADCR_EN_SFT, 0),

687

688 SND_SOC_DAPM_AIF_OUT("AIFTX", "Capture", 0, SND_SOC_NOPM, 0, 0),

689 SND_SOC_DAPM_AIF_IN("AIFRX", "Playback", 0, SND_SOC_NOPM, 0, 0),

690

691 SND_SOC_DAPM_DAC("DACL", NULL, NAU8824_REG_RDAC,

692 NAU8824_DACL_EN_SFT, 0),

693 SND_SOC_DAPM_SUPPLY("DACL Clock", NAU8824_REG_RDAC,

694 NAU8824_DACL_CLK_SFT, 0, NULL, 0),

695 SND_SOC_DAPM_DAC("DACR", NULL, NAU8824_REG_RDAC,

696 NAU8824_DACR_EN_SFT, 0),

697 SND_SOC_DAPM_SUPPLY("DACR Clock", NAU8824_REG_RDAC,

698 NAU8824_DACR_CLK_SFT, 0, NULL, 0),

699

700 SND_SOC_DAPM_MUX("DACL Mux", SND_SOC_NOPM, 0, 0, &nau8824_dacl_mux),

701 SND_SOC_DAPM_MUX("DACR Mux", SND_SOC_NOPM, 0, 0, &nau8824_dacr_mux),

702

703 SND_SOC_DAPM_PGA_S("Output DACL", 0, NAU8824_REG_CHARGE_PUMP_CONTROL,

704 8, 1, nau8824_output_dac_event,

705 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),

706 SND_SOC_DAPM_PGA_S("Output DACR", 0, NAU8824_REG_CHARGE_PUMP_CONTROL,

707 9, 1, nau8824_output_dac_event,

708 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),

709

710 SND_SOC_DAPM_PGA_S("ClassD", 0, NAU8824_REG_CLASSD_GAIN_1,

711 NAU8824_CLASSD_EN_SFT, 0, nau8824_spk_event,

712 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),

713

714 SND_SOC_DAPM_MIXER("Left Headphone", NAU8824_REG_CLASSG,

715 NAU8824_CLASSG_LDAC_EN_SFT, 0, nau8824_hp_left_mixer,

716 ARRAY_SIZE(nau8824_hp_left_mixer)),

717 SND_SOC_DAPM_MIXER("Right Headphone", NAU8824_REG_CLASSG,

718 NAU8824_CLASSG_RDAC_EN_SFT, 0, nau8824_hp_right_mixer,

719 ARRAY_SIZE(nau8824_hp_right_mixer)),

720 SND_SOC_DAPM_PGA_S("Charge Pump", 1, NAU8824_REG_CHARGE_PUMP_CONTROL,

721 NAU8824_CHARGE_PUMP_EN_SFT, 0, nau8824_pump_event,

722 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),

723 SND_SOC_DAPM_PGA("Output Driver L",

724 NAU8824_REG_POWER_UP_CONTROL, 3, 0, NULL, 0),

725 SND_SOC_DAPM_PGA("Output Driver R",

726 NAU8824_REG_POWER_UP_CONTROL, 2, 0, NULL, 0),

727 SND_SOC_DAPM_PGA("Main Driver L",

728 NAU8824_REG_POWER_UP_CONTROL, 1, 0, NULL, 0),

729 SND_SOC_DAPM_PGA("Main Driver R",

730 NAU8824_REG_POWER_UP_CONTROL, 0, 0, NULL, 0),

731 SND_SOC_DAPM_PGA("HP Boost Driver", NAU8824_REG_BOOST,

732 NAU8824_HP_BOOST_DIS_SFT, 1, NULL, 0),

733 SND_SOC_DAPM_PGA("Class G", NAU8824_REG_CLASSG,

734 NAU8824_CLASSG_EN_SFT, 0, NULL, 0),

735

736 SND_SOC_DAPM_OUTPUT("SPKOUTL"),

737 SND_SOC_DAPM_OUTPUT("SPKOUTR"),

738 SND_SOC_DAPM_OUTPUT("HPOL"),

739 SND_SOC_DAPM_OUTPUT("HPOR"),

740 };

741

742 static const struct snd_soc_dapm_route nau8824_dapm_routes[] = {

743 {"DMIC1 Enable", "Switch", "DMIC1"},

744 {"DMIC2 Enable", "Switch", "DMIC2"},

745 {"DMIC3 Enable", "Switch", "DMIC3"},

746 {"DMIC4 Enable", "Switch", "DMIC4"},

747

748 {"DMIC1", NULL, "DMIC12 Power"},

749 {"DMIC2", NULL, "DMIC12 Power"},

750 {"DMIC3", NULL, "DMIC34 Power"},

751 {"DMIC4", NULL, "DMIC34 Power"},

752 {"DMIC12 Power", NULL, "DMIC Clock"},

753 {"DMIC34 Power", NULL, "DMIC Clock"},

754

755 {"Left ADC", "MIC Switch", "MIC1"},

756 {"Left ADC", "HSMIC Switch", "HSMIC1"},

757 {"Right ADC", "MIC Switch", "MIC2"},

758 {"Right ADC", "HSMIC Switch", "HSMIC2"},

759

760 {"ADCL", NULL, "Left ADC"},

761 {"ADCR", NULL, "Right ADC"},

762

763 {"AIFTX", NULL, "MICBIAS"},

764 {"AIFTX", NULL, "ADCL"},

765 {"AIFTX", NULL, "ADCR"},

766 {"AIFTX", NULL, "DMIC1 Enable"},

767 {"AIFTX", NULL, "DMIC2 Enable"},

768 {"AIFTX", NULL, "DMIC3 Enable"},

769 {"AIFTX", NULL, "DMIC4 Enable"},

770

771 {"AIFTX", NULL, "System Clock"},

772 {"AIFRX", NULL, "System Clock"},

773

774 {"DACL", NULL, "AIFRX"},

775 {"DACL", NULL, "DACL Clock"},

776 {"DACR", NULL, "AIFRX"},

777 {"DACR", NULL, "DACR Clock"},

778

779 {"DACL Mux", "DACL", "DACL"},

780 {"DACL Mux", "DACR", "DACR"},

781 {"DACR Mux", "DACL", "DACL"},

782 {"DACR Mux", "DACR", "DACR"},

783

784 {"Output DACL", NULL, "DACL Mux"},

785 {"Output DACR", NULL, "DACR Mux"},

786

787 {"ClassD", NULL, "Output DACL"},

788 {"ClassD", NULL, "Output DACR"},

789

790 {"Left Headphone", "DAC Left Switch", "Output DACL"},

791 {"Left Headphone", "DAC Right Switch", "Output DACR"},

792 {"Right Headphone", "DAC Left Switch", "Output DACL"},

793 {"Right Headphone", "DAC Right Switch", "Output DACR"},

794

795 {"Charge Pump", NULL, "Left Headphone"},

796 {"Charge Pump", NULL, "Right Headphone"},

797 {"Output Driver L", NULL, "Charge Pump"},

798 {"Output Driver R", NULL, "Charge Pump"},

799 {"Main Driver L", NULL, "Output Driver L"},

800 {"Main Driver R", NULL, "Output Driver R"},

801 {"Class G", NULL, "Main Driver L"},

802 {"Class G", NULL, "Main Driver R"},

803 {"HP Boost Driver", NULL, "Class G"},

804

805 {"SPKOUTL", NULL, "ClassD"},

806 {"SPKOUTR", NULL, "ClassD"},

807 {"HPOL", NULL, "HP Boost Driver"},

808 {"HPOR", NULL, "HP Boost Driver"},

809 };

810

811 static bool nau8824_is_jack_inserted(struct nau8824 *nau8824)

812 {

813 struct snd_soc_jack *jack = nau8824->jack;

814 bool insert = false;

815

816 if (nau8824->irq && jack)

817 insert = jack->status & SND_JACK_HEADPHONE;

818

819 return insert;

820 }

821

822 static void nau8824_int_status_clear_all(struct regmap *regmap)

823 {

824 int active_irq, clear_irq, i;

825

826 /* Reset the intrruption status from rightmost bit if the corres-

827 * ponding irq event occurs.

828 */

829 regmap_read(regmap, NAU8824_REG_IRQ, &active_irq);

830 for (i = 0; i < NAU8824_REG_DATA_LEN; i++) {

831 clear_irq = (0x1 << i);

832 if (active_irq & clear_irq)

833 regmap_write(regmap,

834 NAU8824_REG_CLEAR_INT_REG, clear_irq);

835 }

836 }

837

838 static void nau8824_eject_jack(struct nau8824 *nau8824)

839 {

840 struct snd_soc_dapm_context *dapm = nau8824->dapm;

841 struct regmap *regmap = nau8824->regmap;

842

843 /* Clear all interruption status */

844 nau8824_int_status_clear_all(regmap);

845

846 snd_soc_dapm_disable_pin(dapm, "SAR");

847 snd_soc_dapm_disable_pin(dapm, "MICBIAS");

848 snd_soc_dapm_sync(dapm);

849

850 /* Enable the insertion interruption, disable the ejection

851 * interruption, and then bypass de-bounce circuit.

852 */

853 regmap_update_bits(regmap, NAU8824_REG_INTERRUPT_SETTING,

854 NAU8824_IRQ_KEY_RELEASE_DIS | NAU8824_IRQ_KEY_SHORT_PRESS_DIS |

855 NAU8824_IRQ_EJECT_DIS | NAU8824_IRQ_INSERT_DIS,

856 NAU8824_IRQ_KEY_RELEASE_DIS | NAU8824_IRQ_KEY_SHORT_PRESS_DIS |

857 NAU8824_IRQ_EJECT_DIS);

858 regmap_update_bits(regmap, NAU8824_REG_INTERRUPT_SETTING_1,

859 NAU8824_IRQ_INSERT_EN | NAU8824_IRQ_EJECT_EN,

860 NAU8824_IRQ_INSERT_EN);

861 regmap_update_bits(regmap, NAU8824_REG_ENA_CTRL,

862 NAU8824_JD_SLEEP_MODE, NAU8824_JD_SLEEP_MODE);

863

864 /* Close clock for jack type detection at manual mode */

865 if (dapm->bias_level < SND_SOC_BIAS_PREPARE)

866 nau8824_config_sysclk(nau8824, NAU8824_CLK_DIS, 0);

867 }

868

869 static void nau8824_jdet_work(struct work_struct *work)

870 {

871 struct nau8824 *nau8824 = container_of(

872 work, struct nau8824, jdet_work);

873 struct snd_soc_dapm_context *dapm = nau8824->dapm;

874 struct regmap *regmap = nau8824->regmap;

875 int adc_value, event = 0, event_mask = 0;

876

877 snd_soc_dapm_force_enable_pin(dapm, "MICBIAS");

878 snd_soc_dapm_force_enable_pin(dapm, "SAR");

879 snd_soc_dapm_sync(dapm);

880

881 msleep(100);

882

883 regmap_read(regmap, NAU8824_REG_SAR_ADC_DATA_OUT, &adc_value);

884 adc_value = adc_value & NAU8824_SAR_ADC_DATA_MASK;

885 dev_dbg(nau8824->dev, "SAR ADC data 0x%02x\n", adc_value);

886 if (adc_value < HEADSET_SARADC_THD) {

887 event |= SND_JACK_HEADPHONE;

888

889 snd_soc_dapm_disable_pin(dapm, "SAR");

890 snd_soc_dapm_disable_pin(dapm, "MICBIAS");

891 snd_soc_dapm_sync(dapm);

892 } else {

893 event |= SND_JACK_HEADSET;

894 }

895 event_mask |= SND_JACK_HEADSET;

896 snd_soc_jack_report(nau8824->jack, event, event_mask);

897

898 /* Enable short key press and release interruption. */

899 regmap_update_bits(regmap, NAU8824_REG_INTERRUPT_SETTING,

900 NAU8824_IRQ_KEY_RELEASE_DIS |

901 NAU8824_IRQ_KEY_SHORT_PRESS_DIS, 0);

902

903 nau8824_sema_release(nau8824);

904 }

905

906 static void nau8824_setup_auto_irq(struct nau8824 *nau8824)

907 {

908 struct regmap *regmap = nau8824->regmap;

909

910 /* Enable jack ejection interruption. */

911 regmap_update_bits(regmap, NAU8824_REG_INTERRUPT_SETTING_1,

912 NAU8824_IRQ_INSERT_EN | NAU8824_IRQ_EJECT_EN,

913 NAU8824_IRQ_EJECT_EN);

914 regmap_update_bits(regmap, NAU8824_REG_INTERRUPT_SETTING,

915 NAU8824_IRQ_EJECT_DIS, 0);

916 /* Enable internal VCO needed for interruptions */

917 if (nau8824->dapm->bias_level < SND_SOC_BIAS_PREPARE)

918 nau8824_config_sysclk(nau8824, NAU8824_CLK_INTERNAL, 0);

919 regmap_update_bits(regmap, NAU8824_REG_ENA_CTRL,

920 NAU8824_JD_SLEEP_MODE, 0);

921 }

922

923 static int nau8824_button_decode(int value)

924 {

925 int buttons = 0;

926

927 /* The chip supports up to 8 buttons, but ALSA defines

928 * only 6 buttons.

929 */

930 if (value & BIT(0))

931 buttons |= SND_JACK_BTN_0;

932 if (value & BIT(1))

933 buttons |= SND_JACK_BTN_1;

934 if (value & BIT(2))

935 buttons |= SND_JACK_BTN_2;

936 if (value & BIT(3))

937 buttons |= SND_JACK_BTN_3;

938 if (value & BIT(4))

939 buttons |= SND_JACK_BTN_4;

940 if (value & BIT(5))

941 buttons |= SND_JACK_BTN_5;

942

943 return buttons;

944 }

945

946 #define NAU8824_BUTTONS (SND_JACK_BTN_0 | SND_JACK_BTN_1 | \

947 SND_JACK_BTN_2 | SND_JACK_BTN_3)

948

949 static irqreturn_t nau8824_interrupt(int irq, void *data)

950 {

951 struct nau8824 *nau8824 = (struct nau8824 *)data;

952 struct regmap *regmap = nau8824->regmap;

953 int active_irq, clear_irq = 0, event = 0, event_mask = 0;

954

955 if (regmap_read(regmap, NAU8824_REG_IRQ, &active_irq)) {

956 dev_err(nau8824->dev, "failed to read irq status\n");

957 return IRQ_NONE;

958 }

959 dev_dbg(nau8824->dev, "IRQ %x\n", active_irq);

960

961 if (active_irq & NAU8824_JACK_EJECTION_DETECTED) {

962 nau8824_eject_jack(nau8824);

963 event_mask |= SND_JACK_HEADSET;

964 clear_irq = NAU8824_JACK_EJECTION_DETECTED;

965 /* release semaphore held after resume,

966 * and cancel jack detection

967 */

968 nau8824_sema_release(nau8824);

969 cancel_work_sync(&nau8824->jdet_work);

970 } else if (active_irq & NAU8824_KEY_SHORT_PRESS_IRQ) {

971 int key_status, button_pressed;

972

973 regmap_read(regmap, NAU8824_REG_CLEAR_INT_REG,

974 &key_status);

975

976 /* lower 8 bits of the register are for pressed keys */

977 button_pressed = nau8824_button_decode(key_status);

978

979 event |= button_pressed;

980 dev_dbg(nau8824->dev, "button %x pressed\n", event);

981 event_mask |= NAU8824_BUTTONS;

982 clear_irq = NAU8824_KEY_SHORT_PRESS_IRQ;

983 } else if (active_irq & NAU8824_KEY_RELEASE_IRQ) {

984 event_mask = NAU8824_BUTTONS;

985 clear_irq = NAU8824_KEY_RELEASE_IRQ;

986 } else if (active_irq & NAU8824_JACK_INSERTION_DETECTED) {

987 /* Turn off insertion interruption at manual mode */

988 regmap_update_bits(regmap,

989 NAU8824_REG_INTERRUPT_SETTING,

990 NAU8824_IRQ_INSERT_DIS,

991 NAU8824_IRQ_INSERT_DIS);

992 regmap_update_bits(regmap,

993 NAU8824_REG_INTERRUPT_SETTING_1,

994 NAU8824_IRQ_INSERT_EN, 0);

995 /* detect microphone and jack type */

996 cancel_work_sync(&nau8824->jdet_work);

997 schedule_work(&nau8824->jdet_work);

998

999 /* Enable interruption for jack type detection at audo

1000 * mode which can detect microphone and jack type.

1001 */

1002 nau8824_setup_auto_irq(nau8824);

1003 }

1004

1005 if (!clear_irq)

1006 clear_irq = active_irq;

1007 /* clears the rightmost interruption */

1008 regmap_write(regmap, NAU8824_REG_CLEAR_INT_REG, clear_irq);

1009

1010 if (event_mask)

1011 snd_soc_jack_report(nau8824->jack, event, event_mask);

1012

1013 return IRQ_HANDLED;

1014 }

1015

1016 static int nau8824_clock_check(struct nau8824 *nau8824,

1017 int stream, int rate, int osr)

1018 {

1019 int osrate;

1020

1021 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {

1022 if (osr >= ARRAY_SIZE(osr_dac_sel))

1023 return -EINVAL;

1024 osrate = osr_dac_sel[osr].osr;

1025 } else {

1026 if (osr >= ARRAY_SIZE(osr_adc_sel))

1027 return -EINVAL;

1028 osrate = osr_adc_sel[osr].osr;

1029 }

1030

1031 if (!osrate || rate * osr > CLK_DA_AD_MAX) {

1032 dev_err(nau8824->dev, "exceed the maximum frequency of CLK_ADC or CLK_DAC\n");

1033 return -EINVAL;

1034 }

1035

1036 return 0;

1037 }

1038

1039 static int nau8824_hw_params(struct snd_pcm_substream *substream,

1040 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)

1041 {

1042 struct snd_soc_component *component = dai->component;

1043 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);

1044 unsigned int val_len = 0, osr, ctrl_val, bclk_fs, bclk_div;

1045 int err = -EINVAL;

1046

1047 nau8824_sema_acquire(nau8824, HZ);

1048

1049 /* CLK_DAC or CLK_ADC = OSR * FS

1050 * DAC or ADC clock frequency is defined as Over Sampling Rate (OSR)

1051 * multiplied by the audio sample rate (Fs). Note that the OSR and Fs

1052 * values must be selected such that the maximum frequency is less

1053 * than 6.144 MHz.

1054 */

1055 nau8824->fs = params_rate(params);

1056 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {

1057 regmap_read(nau8824->regmap,

1058 NAU8824_REG_DAC_FILTER_CTRL_1, &osr);

1059 osr &= NAU8824_DAC_OVERSAMPLE_MASK;

1060 if (nau8824_clock_check(nau8824, substream->stream,

1061 nau8824->fs, osr))

1062 goto error;

1063 regmap_update_bits(nau8824->regmap, NAU8824_REG_CLK_DIVIDER,

1064 NAU8824_CLK_DAC_SRC_MASK,

1065 osr_dac_sel[osr].clk_src << NAU8824_CLK_DAC_SRC_SFT);

1066 } else {

1067 regmap_read(nau8824->regmap,

1068 NAU8824_REG_ADC_FILTER_CTRL, &osr);

1069 osr &= NAU8824_ADC_SYNC_DOWN_MASK;

1070 if (nau8824_clock_check(nau8824, substream->stream,

1071 nau8824->fs, osr))

1072 goto error;

1073 regmap_update_bits(nau8824->regmap, NAU8824_REG_CLK_DIVIDER,

1074 NAU8824_CLK_ADC_SRC_MASK,

1075 osr_adc_sel[osr].clk_src << NAU8824_CLK_ADC_SRC_SFT);

1076 }

1077

1078 /* make BCLK and LRC divde configuration if the codec as master. */

1079 regmap_read(nau8824->regmap,

1080 NAU8824_REG_PORT0_I2S_PCM_CTRL_2, &ctrl_val);

1081 if (ctrl_val & NAU8824_I2S_MS_MASTER) {

1082 /* get the bclk and fs ratio */

1083 bclk_fs = snd_soc_params_to_bclk(params) / nau8824->fs;

1084 if (bclk_fs <= 32)

1085 bclk_div = 0x3;

1086 else if (bclk_fs <= 64)

1087 bclk_div = 0x2;

1088 else if (bclk_fs <= 128)

1089 bclk_div = 0x1;

1090 else if (bclk_fs <= 256)

1091 bclk_div = 0;

1092 else

1093 goto error;

1094 regmap_update_bits(nau8824->regmap,

1095 NAU8824_REG_PORT0_I2S_PCM_CTRL_2,

1096 NAU8824_I2S_LRC_DIV_MASK | NAU8824_I2S_BLK_DIV_MASK,

1097 (bclk_div << NAU8824_I2S_LRC_DIV_SFT) | bclk_div);

1098 }

1099

1100 switch (params_width(params)) {

1101 case 16:

1102 val_len |= NAU8824_I2S_DL_16;

1103 break;

1104 case 20:

1105 val_len |= NAU8824_I2S_DL_20;

1106 break;

1107 case 24:

1108 val_len |= NAU8824_I2S_DL_24;

1109 break;

1110 case 32:

1111 val_len |= NAU8824_I2S_DL_32;

1112 break;

1113 default:

1114 goto error;

1115 }

1116

1117 regmap_update_bits(nau8824->regmap, NAU8824_REG_PORT0_I2S_PCM_CTRL_1,

1118 NAU8824_I2S_DL_MASK, val_len);

1119 err = 0;

1120

1121 error:

1122 nau8824_sema_release(nau8824);

1123

1124 return err;

1125 }

1126

1127 static int nau8824_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)

1128 {

1129 struct snd_soc_component *component = dai->component;

1130 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);

1131 unsigned int ctrl1_val = 0, ctrl2_val = 0;

1132

1133 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {

1134 case SND_SOC_DAIFMT_CBM_CFM:

1135 ctrl2_val |= NAU8824_I2S_MS_MASTER;

1136 break;

1137 case SND_SOC_DAIFMT_CBS_CFS:

1138 break;

1139 default:

1140 return -EINVAL;

1141 }

1142

1143 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {

1144 case SND_SOC_DAIFMT_NB_NF:

1145 break;

1146 case SND_SOC_DAIFMT_IB_NF:

1147 ctrl1_val |= NAU8824_I2S_BP_INV;

1148 break;

1149 default:

1150 return -EINVAL;

1151 }

1152

1153 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {

1154 case SND_SOC_DAIFMT_I2S:

1155 ctrl1_val |= NAU8824_I2S_DF_I2S;

1156 break;

1157 case SND_SOC_DAIFMT_LEFT_J:

1158 ctrl1_val |= NAU8824_I2S_DF_LEFT;

1159 break;

1160 case SND_SOC_DAIFMT_RIGHT_J:

1161 ctrl1_val |= NAU8824_I2S_DF_RIGTH;

1162 break;

1163 case SND_SOC_DAIFMT_DSP_A:

1164 ctrl1_val |= NAU8824_I2S_DF_PCM_AB;

1165 break;

1166 case SND_SOC_DAIFMT_DSP_B:

1167 ctrl1_val |= NAU8824_I2S_DF_PCM_AB;

1168 ctrl1_val |= NAU8824_I2S_PCMB_EN;

1169 break;

1170 default:

1171 return -EINVAL;

1172 }

1173

1174 nau8824_sema_acquire(nau8824, HZ);

1175

1176 regmap_update_bits(nau8824->regmap, NAU8824_REG_PORT0_I2S_PCM_CTRL_1,

1177 NAU8824_I2S_DF_MASK | NAU8824_I2S_BP_MASK |

1178 NAU8824_I2S_PCMB_EN, ctrl1_val);

1179 regmap_update_bits(nau8824->regmap, NAU8824_REG_PORT0_I2S_PCM_CTRL_2,

1180 NAU8824_I2S_MS_MASK, ctrl2_val);

1181

1182 nau8824_sema_release(nau8824);

1183

1184 return 0;

1185 }

1186

1187 /**

1188 * nau8824_set_tdm_slot - configure DAI TDM.

1189 * @dai: DAI

1190 * @tx_mask: Bitmask representing active TX slots. Ex.

1191 * 0xf for normal 4 channel TDM.

1192 * 0xf0 for shifted 4 channel TDM

1193 * @rx_mask: Bitmask [0:1] representing active DACR RX slots.

1194 * Bitmask [2:3] representing active DACL RX slots.

1195 * 00=CH0,01=CH1,10=CH2,11=CH3. Ex.

1196 * 0xf for DACL/R selecting TDM CH3.

1197 * 0xf0 for DACL/R selecting shifted TDM CH3.

1198 * @slots: Number of slots in use.

1199 * @slot_width: Width in bits for each slot.

1200 *

1201 * Configures a DAI for TDM operation. Only support 4 slots TDM.

1202 */

1203 static int nau8824_set_tdm_slot(struct snd_soc_dai *dai,

1204 unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)

1205 {

1206 struct snd_soc_component *component = dai->component;

1207 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);

1208 unsigned int tslot_l = 0, ctrl_val = 0;

1209

1210 if (slots > 4 || ((tx_mask & 0xf0) && (tx_mask & 0xf)) ||

1211 ((rx_mask & 0xf0) && (rx_mask & 0xf)) ||

1212 ((rx_mask & 0xf0) && (tx_mask & 0xf)) ||

1213 ((rx_mask & 0xf) && (tx_mask & 0xf0)))

1214 return -EINVAL;

1215

1216 ctrl_val |= (NAU8824_TDM_MODE | NAU8824_TDM_OFFSET_EN);

1217 if (tx_mask & 0xf0) {

1218 tslot_l = 4 * slot_width;

1219 ctrl_val |= (tx_mask >> 4);

1220 } else {

1221 ctrl_val |= tx_mask;

1222 }

1223 if (rx_mask & 0xf0)

1224 ctrl_val |= ((rx_mask >> 4) << NAU8824_TDM_DACR_RX_SFT);

1225 else

1226 ctrl_val |= (rx_mask << NAU8824_TDM_DACR_RX_SFT);

1227

1228 regmap_update_bits(nau8824->regmap, NAU8824_REG_TDM_CTRL,

1229 NAU8824_TDM_MODE | NAU8824_TDM_OFFSET_EN |

1230 NAU8824_TDM_DACL_RX_MASK | NAU8824_TDM_DACR_RX_MASK |

1231 NAU8824_TDM_TX_MASK, ctrl_val);

1232 regmap_update_bits(nau8824->regmap, NAU8824_REG_PORT0_LEFT_TIME_SLOT,

1233 NAU8824_TSLOT_L_MASK, tslot_l);

1234

1235 return 0;

1236 }

1237

1238 /**

1239 * nau8824_calc_fll_param - Calculate FLL parameters.

1240 * @fll_in: external clock provided to codec.

1241 * @fs: sampling rate.

1242 * @fll_param: Pointer to structure of FLL parameters.

1243 *

1244 * Calculate FLL parameters to configure codec.

1245 *

1246 * Returns 0 for success or negative error code.

1247 */

1248 static int nau8824_calc_fll_param(unsigned int fll_in,

1249 unsigned int fs, struct nau8824_fll *fll_param)

1250 {

1251 u64 fvco, fvco_max;

1252 unsigned int fref, i, fvco_sel;

1253

1254 /* Ensure the reference clock frequency (FREF) is <= 13.5MHz by dividing

1255 * freq_in by 1, 2, 4, or 8 using FLL pre-scalar.

1256 * FREF = freq_in / NAU8824_FLL_REF_DIV_MASK

1257 */

1258 for (i = 0; i < ARRAY_SIZE(fll_pre_scalar); i++) {

1259 fref = fll_in / fll_pre_scalar[i].param;

1260 if (fref <= NAU_FREF_MAX)

1261 break;

1262 }

1263 if (i == ARRAY_SIZE(fll_pre_scalar))

1264 return -EINVAL;

1265 fll_param->clk_ref_div = fll_pre_scalar[i].val;

1266

1267 /* Choose the FLL ratio based on FREF */

1268 for (i = 0; i < ARRAY_SIZE(fll_ratio); i++) {

1269 if (fref >= fll_ratio[i].param)

1270 break;

1271 }

1272 if (i == ARRAY_SIZE(fll_ratio))

1273 return -EINVAL;

1274 fll_param->ratio = fll_ratio[i].val;

1275

1276 /* Calculate the frequency of DCO (FDCO) given freq_out = 256 * Fs.

1277 * FDCO must be within the 90MHz - 124MHz or the FFL cannot be

1278 * guaranteed across the full range of operation.

1279 * FDCO = freq_out * 2 * mclk_src_scaling

1280 */

1281 fvco_max = 0;

1282 fvco_sel = ARRAY_SIZE(mclk_src_scaling);

1283 for (i = 0; i < ARRAY_SIZE(mclk_src_scaling); i++) {

1284 fvco = 256ULL * fs * 2 * mclk_src_scaling[i].param;

1285 if (fvco > NAU_FVCO_MIN && fvco < NAU_FVCO_MAX &&

1286 fvco_max < fvco) {

1287 fvco_max = fvco;

1288 fvco_sel = i;

1289 }

1290 }

1291 if (ARRAY_SIZE(mclk_src_scaling) == fvco_sel)

1292 return -EINVAL;

1293 fll_param->mclk_src = mclk_src_scaling[fvco_sel].val;

1294

1295 /* Calculate the FLL 10-bit integer input and the FLL 16-bit fractional

1296 * input based on FDCO, FREF and FLL ratio.

1297 */

1298 fvco = div_u64(fvco_max << 16, fref * fll_param->ratio);

1299 fll_param->fll_int = (fvco >> 16) & 0x3FF;

1300 fll_param->fll_frac = fvco & 0xFFFF;

1301 return 0;

1302 }

1303

1304 static void nau8824_fll_apply(struct regmap *regmap,

1305 struct nau8824_fll *fll_param)

1306 {

1307 regmap_update_bits(regmap, NAU8824_REG_CLK_DIVIDER,

1308 NAU8824_CLK_SRC_MASK | NAU8824_CLK_MCLK_SRC_MASK,

1309 NAU8824_CLK_SRC_MCLK | fll_param->mclk_src);

1310 regmap_update_bits(regmap, NAU8824_REG_FLL1,

1311 NAU8824_FLL_RATIO_MASK, fll_param->ratio);

1312 /* FLL 16-bit fractional input */

1313 regmap_write(regmap, NAU8824_REG_FLL2, fll_param->fll_frac);

1314 /* FLL 10-bit integer input */

1315 regmap_update_bits(regmap, NAU8824_REG_FLL3,

1316 NAU8824_FLL_INTEGER_MASK, fll_param->fll_int);

1317 /* FLL pre-scaler */

1318 regmap_update_bits(regmap, NAU8824_REG_FLL4,

1319 NAU8824_FLL_REF_DIV_MASK,

1320 fll_param->clk_ref_div << NAU8824_FLL_REF_DIV_SFT);

1321 /* select divided VCO input */

1322 regmap_update_bits(regmap, NAU8824_REG_FLL5,

1323 NAU8824_FLL_CLK_SW_MASK, NAU8824_FLL_CLK_SW_REF);

1324 /* Disable free-running mode */

1325 regmap_update_bits(regmap,

1326 NAU8824_REG_FLL6, NAU8824_DCO_EN, 0);

1327 if (fll_param->fll_frac) {

1328 regmap_update_bits(regmap, NAU8824_REG_FLL5,

1329 NAU8824_FLL_PDB_DAC_EN | NAU8824_FLL_LOOP_FTR_EN |

1330 NAU8824_FLL_FTR_SW_MASK,

1331 NAU8824_FLL_PDB_DAC_EN | NAU8824_FLL_LOOP_FTR_EN |

1332 NAU8824_FLL_FTR_SW_FILTER);

1333 regmap_update_bits(regmap, NAU8824_REG_FLL6,

1334 NAU8824_SDM_EN, NAU8824_SDM_EN);

1335 } else {

1336 regmap_update_bits(regmap, NAU8824_REG_FLL5,

1337 NAU8824_FLL_PDB_DAC_EN | NAU8824_FLL_LOOP_FTR_EN |

1338 NAU8824_FLL_FTR_SW_MASK, NAU8824_FLL_FTR_SW_ACCU);

1339 regmap_update_bits(regmap,

1340 NAU8824_REG_FLL6, NAU8824_SDM_EN, 0);

1341 }

1342 }

1343

1344 /* freq_out must be 256*Fs in order to achieve the best performance */

1345 static int nau8824_set_pll(struct snd_soc_component *component, int pll_id, int source,

1346 unsigned int freq_in, unsigned int freq_out)

1347 {

1348 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);

1349 struct nau8824_fll fll_param;

1350 int ret, fs;

1351

1352 fs = freq_out / 256;

1353 ret = nau8824_calc_fll_param(freq_in, fs, &fll_param);

1354 if (ret < 0) {

1355 dev_err(nau8824->dev, "Unsupported input clock %d\n", freq_in);

1356 return ret;

1357 }

1358 dev_dbg(nau8824->dev, "mclk_src=%x ratio=%x fll_frac=%x fll_int=%x clk_ref_div=%x\n",

1359 fll_param.mclk_src, fll_param.ratio, fll_param.fll_frac,

1360 fll_param.fll_int, fll_param.clk_ref_div);

1361

1362 nau8824_fll_apply(nau8824->regmap, &fll_param);

1363 mdelay(2);

1364 regmap_update_bits(nau8824->regmap, NAU8824_REG_CLK_DIVIDER,

1365 NAU8824_CLK_SRC_MASK, NAU8824_CLK_SRC_VCO);

1366

1367 return 0;

1368 }

1369

1370 static int nau8824_config_sysclk(struct nau8824 *nau8824,

1371 int clk_id, unsigned int freq)

1372 {

1373 struct regmap *regmap = nau8824->regmap;

1374

1375 switch (clk_id) {

1376 case NAU8824_CLK_DIS:

1377 regmap_update_bits(regmap, NAU8824_REG_CLK_DIVIDER,

1378 NAU8824_CLK_SRC_MASK, NAU8824_CLK_SRC_MCLK);

1379 regmap_update_bits(regmap, NAU8824_REG_FLL6,

1380 NAU8824_DCO_EN, 0);

1381 break;

1382

1383 case NAU8824_CLK_MCLK:

1384 nau8824_sema_acquire(nau8824, HZ);

1385 regmap_update_bits(regmap, NAU8824_REG_CLK_DIVIDER,

1386 NAU8824_CLK_SRC_MASK, NAU8824_CLK_SRC_MCLK);

1387 regmap_update_bits(regmap, NAU8824_REG_FLL6,

1388 NAU8824_DCO_EN, 0);

1389 nau8824_sema_release(nau8824);

1390 break;

1391

1392 case NAU8824_CLK_INTERNAL:

1393 regmap_update_bits(regmap, NAU8824_REG_FLL6,

1394 NAU8824_DCO_EN, NAU8824_DCO_EN);

1395 regmap_update_bits(regmap, NAU8824_REG_CLK_DIVIDER,

1396 NAU8824_CLK_SRC_MASK, NAU8824_CLK_SRC_VCO);

1397 break;

1398

1399 case NAU8824_CLK_FLL_MCLK:

1400 nau8824_sema_acquire(nau8824, HZ);

1401 regmap_update_bits(regmap, NAU8824_REG_FLL3,

1402 NAU8824_FLL_CLK_SRC_MASK, NAU8824_FLL_CLK_SRC_MCLK);

1403 nau8824_sema_release(nau8824);

1404 break;

1405

1406 case NAU8824_CLK_FLL_BLK:

1407 nau8824_sema_acquire(nau8824, HZ);

1408 regmap_update_bits(regmap, NAU8824_REG_FLL3,

1409 NAU8824_FLL_CLK_SRC_MASK, NAU8824_FLL_CLK_SRC_BLK);

1410 nau8824_sema_release(nau8824);

1411 break;

1412

1413 case NAU8824_CLK_FLL_FS:

1414 nau8824_sema_acquire(nau8824, HZ);

1415 regmap_update_bits(regmap, NAU8824_REG_FLL3,

1416 NAU8824_FLL_CLK_SRC_MASK, NAU8824_FLL_CLK_SRC_FS);

1417 nau8824_sema_release(nau8824);

1418 break;

1419

1420 default:

1421 dev_err(nau8824->dev, "Invalid clock id (%d)\n", clk_id);

1422 return -EINVAL;

1423 }

1424

1425 dev_dbg(nau8824->dev, "Sysclk is %dHz and clock id is %d\n", freq,

1426 clk_id);

1427

1428 return 0;

1429 }

1430

1431 static int nau8824_set_sysclk(struct snd_soc_component *component,

1432 int clk_id, int source, unsigned int freq, int dir)

1433 {

1434 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);

1435

1436 return nau8824_config_sysclk(nau8824, clk_id, freq);

1437 }

1438

1439 static void nau8824_resume_setup(struct nau8824 *nau8824)

1440 {

1441 nau8824_config_sysclk(nau8824, NAU8824_CLK_DIS, 0);

1442 if (nau8824->irq) {

1443 /* Clear all interruption status */

1444 nau8824_int_status_clear_all(nau8824->regmap);

1445 /* Enable jack detection at sleep mode, insertion detection,

1446 * and ejection detection.

1447 */

1448 regmap_update_bits(nau8824->regmap, NAU8824_REG_ENA_CTRL,

1449 NAU8824_JD_SLEEP_MODE, NAU8824_JD_SLEEP_MODE);

1450 regmap_update_bits(nau8824->regmap,

1451 NAU8824_REG_INTERRUPT_SETTING_1,

1452 NAU8824_IRQ_EJECT_EN | NAU8824_IRQ_INSERT_EN,

1453 NAU8824_IRQ_EJECT_EN | NAU8824_IRQ_INSERT_EN);

1454 regmap_update_bits(nau8824->regmap,

1455 NAU8824_REG_INTERRUPT_SETTING,

1456 NAU8824_IRQ_EJECT_DIS | NAU8824_IRQ_INSERT_DIS, 0);

1457 }

1458 }

1459

1460 static int nau8824_set_bias_level(struct snd_soc_component *component,

1461 enum snd_soc_bias_level level)

1462 {

1463 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);

1464

1465 switch (level) {

1466 case SND_SOC_BIAS_ON:

1467 break;

1468

1469 case SND_SOC_BIAS_PREPARE:

1470 break;

1471

1472 case SND_SOC_BIAS_STANDBY:

1473 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {

1474 /* Setup codec configuration after resume */

1475 nau8824_resume_setup(nau8824);

1476 }

1477 break;

1478

1479 case SND_SOC_BIAS_OFF:

1480 regmap_update_bits(nau8824->regmap,

1481 NAU8824_REG_INTERRUPT_SETTING, 0x3ff, 0x3ff);

1482 regmap_update_bits(nau8824->regmap,

1483 NAU8824_REG_INTERRUPT_SETTING_1,

1484 NAU8824_IRQ_EJECT_EN | NAU8824_IRQ_INSERT_EN, 0);

1485 break;

1486 }

1487

1488 return 0;

1489 }

1490

1491 static int nau8824_component_probe(struct snd_soc_component *component)

1492 {

1493 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);

1494 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);

1495

1496 nau8824->dapm = dapm;

1497

1498 return 0;

1499 }

1500

1501 static int __maybe_unused nau8824_suspend(struct snd_soc_component *component)

1502 {

1503 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);

1504

1505 if (nau8824->irq) {

1506 disable_irq(nau8824->irq);

1507 snd_soc_component_force_bias_level(component, SND_SOC_BIAS_OFF);

1508 }

1509 regcache_cache_only(nau8824->regmap, true);

1510 regcache_mark_dirty(nau8824->regmap);

1511

1512 return 0;

1513 }

1514

1515 static int __maybe_unused nau8824_resume(struct snd_soc_component *component)

1516 {

1517 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);

1518

1519 regcache_cache_only(nau8824->regmap, false);

1520 regcache_sync(nau8824->regmap);

1521 if (nau8824->irq) {

1522 /* Hold semaphore to postpone playback happening

1523 * until jack detection done.

1524 */

1525 nau8824_sema_acquire(nau8824, 0);

1526 enable_irq(nau8824->irq);

1527 }

1528

1529 return 0;

1530 }

1531

1532 static const struct snd_soc_component_driver nau8824_component_driver = {

1533 .probe = nau8824_component_probe,

1534 .set_sysclk = nau8824_set_sysclk,

1535 .set_pll = nau8824_set_pll,

1536 .set_bias_level = nau8824_set_bias_level,

1537 .suspend = nau8824_suspend,

1538 .resume = nau8824_resume,

1539 .controls = nau8824_snd_controls,

1540 .num_controls = ARRAY_SIZE(nau8824_snd_controls),

1541 .dapm_widgets = nau8824_dapm_widgets,

1542 .num_dapm_widgets = ARRAY_SIZE(nau8824_dapm_widgets),

1543 .dapm_routes = nau8824_dapm_routes,

1544 .num_dapm_routes = ARRAY_SIZE(nau8824_dapm_routes),

1545 .suspend_bias_off = 1,

1546 .idle_bias_on = 1,

1547 .use_pmdown_time = 1,

1548 .endianness = 1,

1549 .non_legacy_dai_naming = 1,

1550 };

1551

1552 static const struct snd_soc_dai_ops nau8824_dai_ops = {

1553 .hw_params = nau8824_hw_params,

1554 .set_fmt = nau8824_set_fmt,

1555 .set_tdm_slot = nau8824_set_tdm_slot,

1556 };

1557

1558 #define NAU8824_RATES SNDRV_PCM_RATE_8000_192000

1559 #define NAU8824_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \

1560 | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)

1561

1562 static struct snd_soc_dai_driver nau8824_dai = {

1563 .name = NAU8824_CODEC_DAI,

1564 .playback = {

1565 .stream_name = "Playback",

1566 .channels_min = 1,

1567 .channels_max = 2,

1568 .rates = NAU8824_RATES,

1569 .formats = NAU8824_FORMATS,

1570 },

1571 .capture = {

1572 .stream_name = "Capture",

1573 .channels_min = 1,

1574 .channels_max = 2,

1575 .rates = NAU8824_RATES,

1576 .formats = NAU8824_FORMATS,

1577 },

1578 .ops = &nau8824_dai_ops,

1579 };

1580

1581 static const struct regmap_config nau8824_regmap_config = {

1582 .val_bits = NAU8824_REG_ADDR_LEN,

1583 .reg_bits = NAU8824_REG_DATA_LEN,

1584

1585 .max_register = NAU8824_REG_MAX,

1586 .readable_reg = nau8824_readable_reg,

1587 .writeable_reg = nau8824_writeable_reg,

1588 .volatile_reg = nau8824_volatile_reg,

1589

1590 .cache_type = REGCACHE_RBTREE,

1591 .reg_defaults = nau8824_reg_defaults,

1592 .num_reg_defaults = ARRAY_SIZE(nau8824_reg_defaults),

1593 };

1594

1595 /**

1596 * nau8824_enable_jack_detect - Specify a jack for event reporting

1597 *

1598 * @component: component to register the jack with

1599 * @jack: jack to use to report headset and button events on

1600 *

1601 * After this function has been called the headset insert/remove and button

1602 * events will be routed to the given jack. Jack can be null to stop

1603 * reporting.

1604 */

1605 int nau8824_enable_jack_detect(struct snd_soc_component *component,

1606 struct snd_soc_jack *jack)

1607 {

1608 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);

1609 int ret;

1610

1611 nau8824->jack = jack;

1612 /* Initiate jack detection work queue */

1613 INIT_WORK(&nau8824->jdet_work, nau8824_jdet_work);

1614 ret = devm_request_threaded_irq(nau8824->dev, nau8824->irq, NULL,

1615 nau8824_interrupt, IRQF_TRIGGER_LOW | IRQF_ONESHOT,

1616 "nau8824", nau8824);

1617 if (ret) {

1618 dev_err(nau8824->dev, "Cannot request irq %d (%d)\n",

1619 nau8824->irq, ret);

1620 }

1621

1622 return ret;

1623 }

1624 EXPORT_SYMBOL_GPL(nau8824_enable_jack_detect);

1625

1626 static void nau8824_reset_chip(struct regmap *regmap)

1627 {

1628 regmap_write(regmap, NAU8824_REG_RESET, 0x00);

1629 regmap_write(regmap, NAU8824_REG_RESET, 0x00);

1630 }

1631

1632 static void nau8824_setup_buttons(struct nau8824 *nau8824)

1633 {

1634 struct regmap *regmap = nau8824->regmap;

1635

1636 regmap_update_bits(regmap, NAU8824_REG_SAR_ADC,

1637 NAU8824_SAR_TRACKING_GAIN_MASK,

1638 nau8824->sar_voltage << NAU8824_SAR_TRACKING_GAIN_SFT);

1639 regmap_update_bits(regmap, NAU8824_REG_SAR_ADC,

1640 NAU8824_SAR_COMPARE_TIME_MASK,

1641 nau8824->sar_compare_time << NAU8824_SAR_COMPARE_TIME_SFT);

1642 regmap_update_bits(regmap, NAU8824_REG_SAR_ADC,

1643 NAU8824_SAR_SAMPLING_TIME_MASK,

1644 nau8824->sar_sampling_time << NAU8824_SAR_SAMPLING_TIME_SFT);

1645

1646 regmap_update_bits(regmap, NAU8824_REG_VDET_COEFFICIENT,

1647 NAU8824_LEVELS_NR_MASK,

1648 (nau8824->sar_threshold_num - 1) << NAU8824_LEVELS_NR_SFT);

1649 regmap_update_bits(regmap, NAU8824_REG_VDET_COEFFICIENT,

1650 NAU8824_HYSTERESIS_MASK,

1651 nau8824->sar_hysteresis << NAU8824_HYSTERESIS_SFT);

1652 regmap_update_bits(regmap, NAU8824_REG_VDET_COEFFICIENT,

1653 NAU8824_SHORTKEY_DEBOUNCE_MASK,

1654 nau8824->key_debounce << NAU8824_SHORTKEY_DEBOUNCE_SFT);

1655

1656 regmap_write(regmap, NAU8824_REG_VDET_THRESHOLD_1,

1657 (nau8824->sar_threshold[0] << 8) | nau8824->sar_threshold[1]);

1658 regmap_write(regmap, NAU8824_REG_VDET_THRESHOLD_2,

1659 (nau8824->sar_threshold[2] << 8) | nau8824->sar_threshold[3]);

1660 regmap_write(regmap, NAU8824_REG_VDET_THRESHOLD_3,

1661 (nau8824->sar_threshold[4] << 8) | nau8824->sar_threshold[5]);

1662 regmap_write(regmap, NAU8824_REG_VDET_THRESHOLD_4,

1663 (nau8824->sar_threshold[6] << 8) | nau8824->sar_threshold[7]);

1664 }

1665

1666 static void nau8824_init_regs(struct nau8824 *nau8824)

1667 {

1668 struct regmap *regmap = nau8824->regmap;

1669

1670 /* Enable Bias/VMID/VMID Tieoff */

1671 regmap_update_bits(regmap, NAU8824_REG_BIAS_ADJ,

1672 NAU8824_VMID | NAU8824_VMID_SEL_MASK, NAU8824_VMID |

1673 (nau8824->vref_impedance << NAU8824_VMID_SEL_SFT));

1674 regmap_update_bits(regmap, NAU8824_REG_BOOST,

1675 NAU8824_GLOBAL_BIAS_EN, NAU8824_GLOBAL_BIAS_EN);

1676 mdelay(2);

1677 regmap_update_bits(regmap, NAU8824_REG_MIC_BIAS,

1678 NAU8824_MICBIAS_VOLTAGE_MASK, nau8824->micbias_voltage);

1679 /* Disable Boost Driver, Automatic Short circuit protection enable */

1680 regmap_update_bits(regmap, NAU8824_REG_BOOST,

1681 NAU8824_PRECHARGE_DIS | NAU8824_HP_BOOST_DIS |

1682 NAU8824_HP_BOOST_G_DIS | NAU8824_SHORT_SHUTDOWN_EN,

1683 NAU8824_PRECHARGE_DIS | NAU8824_HP_BOOST_DIS |

1684 NAU8824_HP_BOOST_G_DIS | NAU8824_SHORT_SHUTDOWN_EN);

1685 /* Scaling for ADC and DAC clock */

1686 regmap_update_bits(regmap, NAU8824_REG_CLK_DIVIDER,

1687 NAU8824_CLK_ADC_SRC_MASK | NAU8824_CLK_DAC_SRC_MASK,

1688 (0x1 << NAU8824_CLK_ADC_SRC_SFT) |

1689 (0x1 << NAU8824_CLK_DAC_SRC_SFT));

1690 regmap_update_bits(regmap, NAU8824_REG_DAC_MUTE_CTRL,

1691 NAU8824_DAC_ZC_EN, NAU8824_DAC_ZC_EN);

1692 regmap_update_bits(regmap, NAU8824_REG_ENA_CTRL,

1693 NAU8824_DAC_CH1_EN | NAU8824_DAC_CH0_EN |

1694 NAU8824_ADC_CH0_EN | NAU8824_ADC_CH1_EN |

1695 NAU8824_ADC_CH2_EN | NAU8824_ADC_CH3_EN,

1696 NAU8824_DAC_CH1_EN | NAU8824_DAC_CH0_EN |

1697 NAU8824_ADC_CH0_EN | NAU8824_ADC_CH1_EN |

1698 NAU8824_ADC_CH2_EN | NAU8824_ADC_CH3_EN);

1699 regmap_update_bits(regmap, NAU8824_REG_CLK_GATING_ENA,

1700 NAU8824_CLK_ADC_CH23_EN | NAU8824_CLK_ADC_CH01_EN |

1701 NAU8824_CLK_DAC_CH1_EN | NAU8824_CLK_DAC_CH0_EN |

1702 NAU8824_CLK_I2S_EN | NAU8824_CLK_GAIN_EN |

1703 NAU8824_CLK_SAR_EN | NAU8824_CLK_DMIC_CH23_EN,

1704 NAU8824_CLK_ADC_CH23_EN | NAU8824_CLK_ADC_CH01_EN |

1705 NAU8824_CLK_DAC_CH1_EN | NAU8824_CLK_DAC_CH0_EN |

1706 NAU8824_CLK_I2S_EN | NAU8824_CLK_GAIN_EN |

1707 NAU8824_CLK_SAR_EN | NAU8824_CLK_DMIC_CH23_EN);

1708 /* Class G timer 64ms */

1709 regmap_update_bits(regmap, NAU8824_REG_CLASSG,

1710 NAU8824_CLASSG_TIMER_MASK,

1711 0x20 << NAU8824_CLASSG_TIMER_SFT);

1712 regmap_update_bits(regmap, NAU8824_REG_TRIM_SETTINGS,

1713 NAU8824_DRV_CURR_INC, NAU8824_DRV_CURR_INC);

1714 /* Disable DACR/L power */

1715 regmap_update_bits(regmap, NAU8824_REG_CHARGE_PUMP_CONTROL,

1716 NAU8824_SPKR_PULL_DOWN | NAU8824_SPKL_PULL_DOWN |

1717 NAU8824_POWER_DOWN_DACR | NAU8824_POWER_DOWN_DACL,

1718 NAU8824_SPKR_PULL_DOWN | NAU8824_SPKL_PULL_DOWN |

1719 NAU8824_POWER_DOWN_DACR | NAU8824_POWER_DOWN_DACL);

1720 /* Enable TESTDAC. This sets the analog DAC inputs to a '0' input

1721 * signal to avoid any glitches due to power up transients in both

1722 * the analog and digital DAC circuit.

1723 */

1724 regmap_update_bits(regmap, NAU8824_REG_ENABLE_LO,

1725 NAU8824_TEST_DAC_EN, NAU8824_TEST_DAC_EN);

1726 /* Config L/R channel */

1727 regmap_update_bits(regmap, NAU8824_REG_DAC_CH0_DGAIN_CTRL,

1728 NAU8824_DAC_CH0_SEL_MASK, NAU8824_DAC_CH0_SEL_I2S0);

1729 regmap_update_bits(regmap, NAU8824_REG_DAC_CH1_DGAIN_CTRL,

1730 NAU8824_DAC_CH1_SEL_MASK, NAU8824_DAC_CH1_SEL_I2S1);

1731 regmap_update_bits(regmap, NAU8824_REG_ENABLE_LO,

1732 NAU8824_DACR_HPR_EN | NAU8824_DACL_HPL_EN,

1733 NAU8824_DACR_HPR_EN | NAU8824_DACL_HPL_EN);

1734 /* Default oversampling/decimations settings are unusable

1735 * (audible hiss). Set it to something better.

1736 */

1737 regmap_update_bits(regmap, NAU8824_REG_ADC_FILTER_CTRL,

1738 NAU8824_ADC_SYNC_DOWN_MASK, NAU8824_ADC_SYNC_DOWN_64);

1739 regmap_update_bits(regmap, NAU8824_REG_DAC_FILTER_CTRL_1,

1740 NAU8824_DAC_CICCLP_OFF | NAU8824_DAC_OVERSAMPLE_MASK,

1741 NAU8824_DAC_CICCLP_OFF | NAU8824_DAC_OVERSAMPLE_64);

1742 /* DAC clock delay 2ns, VREF */

1743 regmap_update_bits(regmap, NAU8824_REG_RDAC,

1744 NAU8824_RDAC_CLK_DELAY_MASK | NAU8824_RDAC_VREF_MASK,

1745 (0x2 << NAU8824_RDAC_CLK_DELAY_SFT) |

1746 (0x3 << NAU8824_RDAC_VREF_SFT));

1747 /* PGA input mode selection */

1748 regmap_update_bits(regmap, NAU8824_REG_FEPGA,

1749 NAU8824_FEPGA_MODEL_SHORT_EN | NAU8824_FEPGA_MODER_SHORT_EN,

1750 NAU8824_FEPGA_MODEL_SHORT_EN | NAU8824_FEPGA_MODER_SHORT_EN);

1751 /* Digital microphone control */

1752 regmap_update_bits(regmap, NAU8824_REG_ANALOG_CONTROL_1,

1753 NAU8824_DMIC_CLK_DRV_STRG | NAU8824_DMIC_CLK_SLEW_FAST,

1754 NAU8824_DMIC_CLK_DRV_STRG | NAU8824_DMIC_CLK_SLEW_FAST);

1755 regmap_update_bits(regmap, NAU8824_REG_JACK_DET_CTRL,

1756 NAU8824_JACK_LOGIC,

1757 /* jkdet_polarity - 1 is for active-low */

1758 nau8824->jkdet_polarity ? 0 : NAU8824_JACK_LOGIC);

1759 regmap_update_bits(regmap,

1760 NAU8824_REG_JACK_DET_CTRL, NAU8824_JACK_EJECT_DT_MASK,

1761 (nau8824->jack_eject_debounce << NAU8824_JACK_EJECT_DT_SFT));

1762 if (nau8824->sar_threshold_num)

1763 nau8824_setup_buttons(nau8824);

1764 }

1765

1766 static int nau8824_setup_irq(struct nau8824 *nau8824)

1767 {

1768 /* Disable interruption before codec initiation done */

1769 regmap_update_bits(nau8824->regmap, NAU8824_REG_ENA_CTRL,

1770 NAU8824_JD_SLEEP_MODE, NAU8824_JD_SLEEP_MODE);

1771 regmap_update_bits(nau8824->regmap,

1772 NAU8824_REG_INTERRUPT_SETTING, 0x3ff, 0x3ff);

1773 regmap_update_bits(nau8824->regmap, NAU8824_REG_INTERRUPT_SETTING_1,

1774 NAU8824_IRQ_EJECT_EN | NAU8824_IRQ_INSERT_EN, 0);

1775

1776 return 0;

1777 }

1778

1779 static void nau8824_print_device_properties(struct nau8824 *nau8824)

1780 {

1781 struct device *dev = nau8824->dev;

1782 int i;

1783

1784 dev_dbg(dev, "jkdet-polarity: %d\n", nau8824->jkdet_polarity);

1785 dev_dbg(dev, "micbias-voltage: %d\n", nau8824->micbias_voltage);

1786 dev_dbg(dev, "vref-impedance: %d\n", nau8824->vref_impedance);

1787

1788 dev_dbg(dev, "sar-threshold-num: %d\n", nau8824->sar_threshold_num);

1789 for (i = 0; i < nau8824->sar_threshold_num; i++)

1790 dev_dbg(dev, "sar-threshold[%d]=%x\n", i,

1791 nau8824->sar_threshold[i]);

1792

1793 dev_dbg(dev, "sar-hysteresis: %d\n", nau8824->sar_hysteresis);

1794 dev_dbg(dev, "sar-voltage: %d\n", nau8824->sar_voltage);

1795 dev_dbg(dev, "sar-compare-time: %d\n", nau8824->sar_compare_time);

1796 dev_dbg(dev, "sar-sampling-time: %d\n", nau8824->sar_sampling_time);

1797 dev_dbg(dev, "short-key-debounce: %d\n", nau8824->key_debounce);

1798 dev_dbg(dev, "jack-eject-debounce: %d\n",

1799 nau8824->jack_eject_debounce);

1800 }

1801

1802 static int nau8824_read_device_properties(struct device *dev,

1803 struct nau8824 *nau8824) {

1804 int ret;

1805

1806 ret = device_property_read_u32(dev, "nuvoton,jkdet-polarity",

1807 &nau8824->jkdet_polarity);

1808 if (ret)

1809 nau8824->jkdet_polarity = 1;

1810 ret = device_property_read_u32(dev, "nuvoton,micbias-voltage",

1811 &nau8824->micbias_voltage);

1812 if (ret)

1813 nau8824->micbias_voltage = 6;

1814 ret = device_property_read_u32(dev, "nuvoton,vref-impedance",

1815 &nau8824->vref_impedance);

1816 if (ret)

1817 nau8824->vref_impedance = 2;

1818 ret = device_property_read_u32(dev, "nuvoton,sar-threshold-num",

1819 &nau8824->sar_threshold_num);

1820 if (ret)

1821 nau8824->sar_threshold_num = 4;

1822 ret = device_property_read_u32_array(dev, "nuvoton,sar-threshold",

1823 nau8824->sar_threshold, nau8824->sar_threshold_num);

1824 if (ret) {

1825 nau8824->sar_threshold[0] = 0x0a;

1826 nau8824->sar_threshold[1] = 0x14;

1827 nau8824->sar_threshold[2] = 0x26;

1828 nau8824->sar_threshold[3] = 0x73;

1829 }

1830 ret = device_property_read_u32(dev, "nuvoton,sar-hysteresis",

1831 &nau8824->sar_hysteresis);

1832 if (ret)

1833 nau8824->sar_hysteresis = 0;

1834 ret = device_property_read_u32(dev, "nuvoton,sar-voltage",

1835 &nau8824->sar_voltage);

1836 if (ret)

1837 nau8824->sar_voltage = 6;

1838 ret = device_property_read_u32(dev, "nuvoton,sar-compare-time",

1839 &nau8824->sar_compare_time);

1840 if (ret)

1841 nau8824->sar_compare_time = 1;

1842 ret = device_property_read_u32(dev, "nuvoton,sar-sampling-time",

1843 &nau8824->sar_sampling_time);

1844 if (ret)

1845 nau8824->sar_sampling_time = 1;

1846 ret = device_property_read_u32(dev, "nuvoton,short-key-debounce",

1847 &nau8824->key_debounce);

1848 if (ret)

1849 nau8824->key_debounce = 0;

1850 ret = device_property_read_u32(dev, "nuvoton,jack-eject-debounce",

1851 &nau8824->jack_eject_debounce);

1852 if (ret)

1853 nau8824->jack_eject_debounce = 1;

1854

1855 return 0;

1856 }

1857

1858 /* Please keep this list alphabetically sorted */

1859 static const struct dmi_system_id nau8824_quirk_table[] = {

1860 {

1861 /* Cyberbook T116 rugged tablet */

1862 .matches = {

1863 DMI_EXACT_MATCH(DMI_BOARD_VENDOR, "Default string"),

1864 DMI_EXACT_MATCH(DMI_BOARD_NAME, "Cherry Trail CR"),

1865 DMI_EXACT_MATCH(DMI_PRODUCT_SKU, "20170531"),

1866 },

1867 .driver_data = (void *)(NAU8824_JD_ACTIVE_HIGH),

1868 },

1869 {}

1870 };

1871

1872 static void nau8824_check_quirks(void)

1873 {

1874 const struct dmi_system_id *dmi_id;

1875

1876 if (quirk_override != -1) {

1877 nau8824_quirk = quirk_override;

1878 return;

1879 }

1880

1881 dmi_id = dmi_first_match(nau8824_quirk_table);

1882 if (dmi_id)

1883 nau8824_quirk = (unsigned long)dmi_id->driver_data;

1884 }

1885

1886 static int nau8824_i2c_probe(struct i2c_client *i2c,

1887 const struct i2c_device_id *id)

1888 {

1889 struct device *dev = &i2c->dev;

1890 struct nau8824 *nau8824 = dev_get_platdata(dev);

1891 int ret, value;

1892

1893 if (!nau8824) {

1894 nau8824 = devm_kzalloc(dev, sizeof(*nau8824), GFP_KERNEL);

1895 if (!nau8824)

1896 return -ENOMEM;

1897 ret = nau8824_read_device_properties(dev, nau8824);

1898 if (ret)

1899 return ret;

1900 }

1901 i2c_set_clientdata(i2c, nau8824);

1902

1903 nau8824->regmap = devm_regmap_init_i2c(i2c, &nau8824_regmap_config);

1904 if (IS_ERR(nau8824->regmap))

1905 return PTR_ERR(nau8824->regmap);

1906 nau8824->dev = dev;

1907 nau8824->irq = i2c->irq;

1908 sema_init(&nau8824->jd_sem, 1);

1909

1910 nau8824_check_quirks();

1911

1912 if (nau8824_quirk & NAU8824_JD_ACTIVE_HIGH)

1913 nau8824->jkdet_polarity = 0;

1914

1915 nau8824_print_device_properties(nau8824);

1916

1917 ret = regmap_read(nau8824->regmap, NAU8824_REG_I2C_DEVICE_ID, &value);

1918 if (ret < 0) {

1919 dev_err(dev, "Failed to read device id from the NAU8824: %d\n",

1920 ret);

1921 return ret;

1922 }

1923 nau8824_reset_chip(nau8824->regmap);

1924 nau8824_init_regs(nau8824);

1925

1926 if (i2c->irq)

1927 nau8824_setup_irq(nau8824);

1928

1929 return devm_snd_soc_register_component(dev,

1930 &nau8824_component_driver, &nau8824_dai, 1);

1931 }

1932

1933 static const struct i2c_device_id nau8824_i2c_ids[] = {

1934 { "nau8824", 0 },

1935 { }

1936 };

1937 MODULE_DEVICE_TABLE(i2c, nau8824_i2c_ids);

1938

1939 #ifdef CONFIG_OF

1940 static const struct of_device_id nau8824_of_ids[] = {

1941 { .compatible = "nuvoton,nau8824", },

1942 {}

1943 };

1944 MODULE_DEVICE_TABLE(of, nau8824_of_ids);

1945 #endif

1946

1947 #ifdef CONFIG_ACPI

1948 static const struct acpi_device_id nau8824_acpi_match[] = {

1949 { "10508824", 0 },

1950 {},

1951 };

1952 MODULE_DEVICE_TABLE(acpi, nau8824_acpi_match);

1953 #endif

1954

1955 static struct i2c_driver nau8824_i2c_driver = {

1956 .driver = {

1957 .name = "nau8824",

1958 .of_match_table = of_match_ptr(nau8824_of_ids),

1959 .acpi_match_table = ACPI_PTR(nau8824_acpi_match),

1960 },

1961 .probe = nau8824_i2c_probe,

1962 .id_table = nau8824_i2c_ids,

1963 };

1964 module_i2c_driver(nau8824_i2c_driver);

1965

1966

1967 MODULE_DESCRIPTION("ASoC NAU88L24 driver");

1968 MODULE_AUTHOR("John Hsu <KCHSU0@nuvoton.com>");

1969 MODULE_LICENSE("GPL v2");