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1 /* SPDX-License-Identifier: GPL-2.0-only */

2 /*

4 */

5

6 #ifndef _ASM_RISCV_CSR_H

7 #define _ASM_RISCV_CSR_H

8

9 #include <asm/asm.h>

10 #include <linux/bits.h>

11

12 /* Status register flags */

13 #define SR_SIE _AC(0x00000002, UL) /* Supervisor Interrupt Enable */

14 #define SR_MIE _AC(0x00000008, UL) /* Machine Interrupt Enable */

15 #define SR_SPIE _AC(0x00000020, UL) /* Previous Supervisor IE */

16 #define SR_MPIE _AC(0x00000080, UL) /* Previous Machine IE */

17 #define SR_SPP _AC(0x00000100, UL) /* Previously Supervisor */

18 #define SR_MPP _AC(0x00001800, UL) /* Previously Machine */

19 #define SR_SUM _AC(0x00040000, UL) /* Supervisor User Memory Access */

20

21 #define SR_FS _AC(0x00006000, UL) /* Floating-point Status */

22 #define SR_FS_OFF _AC(0x00000000, UL)

23 #define SR_FS_INITIAL _AC(0x00002000, UL)

24 #define SR_FS_CLEAN _AC(0x00004000, UL)

25 #define SR_FS_DIRTY _AC(0x00006000, UL)

26

27 #define SR_XS _AC(0x00018000, UL) /* Extension Status */

28 #define SR_XS_OFF _AC(0x00000000, UL)

29 #define SR_XS_INITIAL _AC(0x00008000, UL)

30 #define SR_XS_CLEAN _AC(0x00010000, UL)

31 #define SR_XS_DIRTY _AC(0x00018000, UL)

32

33 #ifndef CONFIG_64BIT

34 #define SR_SD _AC(0x80000000, UL) /* FS/XS dirty */

35 #else

36 #define SR_SD _AC(0x8000000000000000, UL) /* FS/XS dirty */

37 #endif

38

39 #ifdef CONFIG_64BIT

40 #define SR_UXL _AC(0x300000000, UL) /* XLEN mask for U-mode */

41 #define SR_UXL_32 _AC(0x100000000, UL) /* XLEN = 32 for U-mode */

42 #define SR_UXL_64 _AC(0x200000000, UL) /* XLEN = 64 for U-mode */

43 #define SR_UXL_SHIFT 32

44 #endif

45

46 /* SATP flags */

47 #ifndef CONFIG_64BIT

48 #define SATP_PPN _AC(0x003FFFFF, UL)

49 #define SATP_MODE_32 _AC(0x80000000, UL)

50 #define SATP_ASID_BITS 9

51 #define SATP_ASID_SHIFT 22

52 #define SATP_ASID_MASK _AC(0x1FF, UL)

53 #else

54 #define SATP_PPN _AC(0x00000FFFFFFFFFFF, UL)

55 #define SATP_MODE_39 _AC(0x8000000000000000, UL)

56 #define SATP_MODE_48 _AC(0x9000000000000000, UL)

57 #define SATP_MODE_57 _AC(0xa000000000000000, UL)

58 #define SATP_ASID_BITS 16

59 #define SATP_ASID_SHIFT 44

60 #define SATP_ASID_MASK _AC(0xFFFF, UL)

61 #endif

62

63 /* Exception cause high bit - is an interrupt if set */

64 #define CAUSE_IRQ_FLAG (_AC(1, UL) << (__riscv_xlen - 1))

65

66 /* Interrupt causes (minus the high bit) */

67 #define IRQ_S_SOFT 1

68 #define IRQ_VS_SOFT 2

69 #define IRQ_M_SOFT 3

70 #define IRQ_S_TIMER 5

71 #define IRQ_VS_TIMER 6

72 #define IRQ_M_TIMER 7

73 #define IRQ_S_EXT 9

74 #define IRQ_VS_EXT 10

75 #define IRQ_M_EXT 11

76 #define IRQ_S_GEXT 12

77 #define IRQ_PMU_OVF 13

78 #define IRQ_LOCAL_MAX (IRQ_PMU_OVF + 1)

79 #define IRQ_LOCAL_MASK GENMASK((IRQ_LOCAL_MAX - 1), 0)

80

81 /* Exception causes */

82 #define EXC_INST_MISALIGNED 0

83 #define EXC_INST_ACCESS 1

84 #define EXC_INST_ILLEGAL 2

85 #define EXC_BREAKPOINT 3

86 #define EXC_LOAD_ACCESS 5

87 #define EXC_STORE_ACCESS 7

88 #define EXC_SYSCALL 8

89 #define EXC_HYPERVISOR_SYSCALL 9

90 #define EXC_SUPERVISOR_SYSCALL 10

91 #define EXC_INST_PAGE_FAULT 12

92 #define EXC_LOAD_PAGE_FAULT 13

93 #define EXC_STORE_PAGE_FAULT 15

94 #define EXC_INST_GUEST_PAGE_FAULT 20

95 #define EXC_LOAD_GUEST_PAGE_FAULT 21

96 #define EXC_VIRTUAL_INST_FAULT 22

97 #define EXC_STORE_GUEST_PAGE_FAULT 23

98

99 /* PMP configuration */

100 #define PMP_R 0x01

101 #define PMP_W 0x02

102 #define PMP_X 0x04

103 #define PMP_A 0x18

104 #define PMP_A_TOR 0x08

105 #define PMP_A_NA4 0x10

106 #define PMP_A_NAPOT 0x18

107 #define PMP_L 0x80

108

109 /* HSTATUS flags */

110 #ifdef CONFIG_64BIT

111 #define HSTATUS_VSXL _AC(0x300000000, UL)

112 #define HSTATUS_VSXL_SHIFT 32

113 #endif

114 #define HSTATUS_VTSR _AC(0x00400000, UL)

115 #define HSTATUS_VTW _AC(0x00200000, UL)

116 #define HSTATUS_VTVM _AC(0x00100000, UL)

117 #define HSTATUS_VGEIN _AC(0x0003f000, UL)

118 #define HSTATUS_VGEIN_SHIFT 12

119 #define HSTATUS_HU _AC(0x00000200, UL)

120 #define HSTATUS_SPVP _AC(0x00000100, UL)

121 #define HSTATUS_SPV _AC(0x00000080, UL)

122 #define HSTATUS_GVA _AC(0x00000040, UL)

123 #define HSTATUS_VSBE _AC(0x00000020, UL)

124

125 /* HGATP flags */

126 #define HGATP_MODE_OFF _AC(0, UL)

127 #define HGATP_MODE_SV32X4 _AC(1, UL)

128 #define HGATP_MODE_SV39X4 _AC(8, UL)

129 #define HGATP_MODE_SV48X4 _AC(9, UL)

130 #define HGATP_MODE_SV57X4 _AC(10, UL)

131

132 #define HGATP32_MODE_SHIFT 31

133 #define HGATP32_VMID_SHIFT 22

134 #define HGATP32_VMID GENMASK(28, 22)

135 #define HGATP32_PPN GENMASK(21, 0)

136

137 #define HGATP64_MODE_SHIFT 60

138 #define HGATP64_VMID_SHIFT 44

139 #define HGATP64_VMID GENMASK(57, 44)

140 #define HGATP64_PPN GENMASK(43, 0)

141

142 #define HGATP_PAGE_SHIFT 12

143

144 #ifdef CONFIG_64BIT

145 #define HGATP_PPN HGATP64_PPN

146 #define HGATP_VMID_SHIFT HGATP64_VMID_SHIFT

147 #define HGATP_VMID HGATP64_VMID

148 #define HGATP_MODE_SHIFT HGATP64_MODE_SHIFT

149 #else

150 #define HGATP_PPN HGATP32_PPN

151 #define HGATP_VMID_SHIFT HGATP32_VMID_SHIFT

152 #define HGATP_VMID HGATP32_VMID

153 #define HGATP_MODE_SHIFT HGATP32_MODE_SHIFT

154 #endif

155

156 /* VSIP & HVIP relation */

157 #define VSIP_TO_HVIP_SHIFT (IRQ_VS_SOFT - IRQ_S_SOFT)

158 #define VSIP_VALID_MASK ((_AC(1, UL) << IRQ_S_SOFT) | \

159 (_AC(1, UL) << IRQ_S_TIMER) | \

160 (_AC(1, UL) << IRQ_S_EXT))

161

162 /* AIA CSR bits */

163 #define TOPI_IID_SHIFT 16

164 #define TOPI_IID_MASK GENMASK(11, 0)

165 #define TOPI_IPRIO_MASK GENMASK(7, 0)

166 #define TOPI_IPRIO_BITS 8

167

168 #define TOPEI_ID_SHIFT 16

169 #define TOPEI_ID_MASK GENMASK(10, 0)

170 #define TOPEI_PRIO_MASK GENMASK(10, 0)

171

172 #define ISELECT_IPRIO0 0x30

173 #define ISELECT_IPRIO15 0x3f

174 #define ISELECT_MASK GENMASK(8, 0)

175

176 #define HVICTL_VTI BIT(30)

177 #define HVICTL_IID GENMASK(27, 16)

178 #define HVICTL_IID_SHIFT 16

179 #define HVICTL_DPR BIT(9)

180 #define HVICTL_IPRIOM BIT(8)

181 #define HVICTL_IPRIO GENMASK(7, 0)

182

183 /* xENVCFG flags */

184 #define ENVCFG_STCE (_AC(1, ULL) << 63)

185 #define ENVCFG_PBMTE (_AC(1, ULL) << 62)

186 #define ENVCFG_CBZE (_AC(1, UL) << 7)

187 #define ENVCFG_CBCFE (_AC(1, UL) << 6)

188 #define ENVCFG_CBIE_SHIFT 4

189 #define ENVCFG_CBIE (_AC(0x3, UL) << ENVCFG_CBIE_SHIFT)

190 #define ENVCFG_CBIE_ILL _AC(0x0, UL)

191 #define ENVCFG_CBIE_FLUSH _AC(0x1, UL)

192 #define ENVCFG_CBIE_INV _AC(0x3, UL)

193 #define ENVCFG_FIOM _AC(0x1, UL)

194

195 /* symbolic CSR names: */

196 #define CSR_CYCLE 0xc00

197 #define CSR_TIME 0xc01

198 #define CSR_INSTRET 0xc02

199 #define CSR_HPMCOUNTER3 0xc03

200 #define CSR_HPMCOUNTER4 0xc04

201 #define CSR_HPMCOUNTER5 0xc05

202 #define CSR_HPMCOUNTER6 0xc06

203 #define CSR_HPMCOUNTER7 0xc07

204 #define CSR_HPMCOUNTER8 0xc08

205 #define CSR_HPMCOUNTER9 0xc09

206 #define CSR_HPMCOUNTER10 0xc0a

207 #define CSR_HPMCOUNTER11 0xc0b

208 #define CSR_HPMCOUNTER12 0xc0c

209 #define CSR_HPMCOUNTER13 0xc0d

210 #define CSR_HPMCOUNTER14 0xc0e

211 #define CSR_HPMCOUNTER15 0xc0f

212 #define CSR_HPMCOUNTER16 0xc10

213 #define CSR_HPMCOUNTER17 0xc11

214 #define CSR_HPMCOUNTER18 0xc12

215 #define CSR_HPMCOUNTER19 0xc13

216 #define CSR_HPMCOUNTER20 0xc14

217 #define CSR_HPMCOUNTER21 0xc15

218 #define CSR_HPMCOUNTER22 0xc16

219 #define CSR_HPMCOUNTER23 0xc17

220 #define CSR_HPMCOUNTER24 0xc18

221 #define CSR_HPMCOUNTER25 0xc19

222 #define CSR_HPMCOUNTER26 0xc1a

223 #define CSR_HPMCOUNTER27 0xc1b

224 #define CSR_HPMCOUNTER28 0xc1c

225 #define CSR_HPMCOUNTER29 0xc1d

226 #define CSR_HPMCOUNTER30 0xc1e

227 #define CSR_HPMCOUNTER31 0xc1f

228 #define CSR_CYCLEH 0xc80

229 #define CSR_TIMEH 0xc81

230 #define CSR_INSTRETH 0xc82

231 #define CSR_HPMCOUNTER3H 0xc83

232 #define CSR_HPMCOUNTER4H 0xc84

233 #define CSR_HPMCOUNTER5H 0xc85

234 #define CSR_HPMCOUNTER6H 0xc86

235 #define CSR_HPMCOUNTER7H 0xc87

236 #define CSR_HPMCOUNTER8H 0xc88

237 #define CSR_HPMCOUNTER9H 0xc89

238 #define CSR_HPMCOUNTER10H 0xc8a

239 #define CSR_HPMCOUNTER11H 0xc8b

240 #define CSR_HPMCOUNTER12H 0xc8c

241 #define CSR_HPMCOUNTER13H 0xc8d

242 #define CSR_HPMCOUNTER14H 0xc8e

243 #define CSR_HPMCOUNTER15H 0xc8f

244 #define CSR_HPMCOUNTER16H 0xc90

245 #define CSR_HPMCOUNTER17H 0xc91

246 #define CSR_HPMCOUNTER18H 0xc92

247 #define CSR_HPMCOUNTER19H 0xc93

248 #define CSR_HPMCOUNTER20H 0xc94

249 #define CSR_HPMCOUNTER21H 0xc95

250 #define CSR_HPMCOUNTER22H 0xc96

251 #define CSR_HPMCOUNTER23H 0xc97

252 #define CSR_HPMCOUNTER24H 0xc98

253 #define CSR_HPMCOUNTER25H 0xc99

254 #define CSR_HPMCOUNTER26H 0xc9a

255 #define CSR_HPMCOUNTER27H 0xc9b

256 #define CSR_HPMCOUNTER28H 0xc9c

257 #define CSR_HPMCOUNTER29H 0xc9d

258 #define CSR_HPMCOUNTER30H 0xc9e

259 #define CSR_HPMCOUNTER31H 0xc9f

260

261 #define CSR_SSCOUNTOVF 0xda0

262

263 #define CSR_SSTATUS 0x100

264 #define CSR_SIE 0x104

265 #define CSR_STVEC 0x105

266 #define CSR_SCOUNTEREN 0x106

267 #define CSR_SSCRATCH 0x140

268 #define CSR_SEPC 0x141

269 #define CSR_SCAUSE 0x142

270 #define CSR_STVAL 0x143

271 #define CSR_SIP 0x144

272 #define CSR_SATP 0x180

273

274 #define CSR_STIMECMP 0x14D

275 #define CSR_STIMECMPH 0x15D

276

277 /* Supervisor-Level Window to Indirectly Accessed Registers (AIA) */

278 #define CSR_SISELECT 0x150

279 #define CSR_SIREG 0x151

280

281 /* Supervisor-Level Interrupts (AIA) */

282 #define CSR_STOPEI 0x15c

283 #define CSR_STOPI 0xdb0

284

285 /* Supervisor-Level High-Half CSRs (AIA) */

286 #define CSR_SIEH 0x114

287 #define CSR_SIPH 0x154

288

289 #define CSR_VSSTATUS 0x200

290 #define CSR_VSIE 0x204

291 #define CSR_VSTVEC 0x205

292 #define CSR_VSSCRATCH 0x240

293 #define CSR_VSEPC 0x241

294 #define CSR_VSCAUSE 0x242

295 #define CSR_VSTVAL 0x243

296 #define CSR_VSIP 0x244

297 #define CSR_VSATP 0x280

298 #define CSR_VSTIMECMP 0x24D

299 #define CSR_VSTIMECMPH 0x25D

300

301 #define CSR_HSTATUS 0x600

302 #define CSR_HEDELEG 0x602

303 #define CSR_HIDELEG 0x603

304 #define CSR_HIE 0x604

305 #define CSR_HTIMEDELTA 0x605

306 #define CSR_HCOUNTEREN 0x606

307 #define CSR_HGEIE 0x607

308 #define CSR_HENVCFG 0x60a

309 #define CSR_HTIMEDELTAH 0x615

310 #define CSR_HENVCFGH 0x61a

311 #define CSR_HTVAL 0x643

312 #define CSR_HIP 0x644

313 #define CSR_HVIP 0x645

314 #define CSR_HTINST 0x64a

315 #define CSR_HGATP 0x680

316 #define CSR_HGEIP 0xe12

317

318 /* Virtual Interrupts and Interrupt Priorities (H-extension with AIA) */

319 #define CSR_HVIEN 0x608

320 #define CSR_HVICTL 0x609

321 #define CSR_HVIPRIO1 0x646

322 #define CSR_HVIPRIO2 0x647

323

324 /* VS-Level Window to Indirectly Accessed Registers (H-extension with AIA) */

325 #define CSR_VSISELECT 0x250

326 #define CSR_VSIREG 0x251

327

328 /* VS-Level Interrupts (H-extension with AIA) */

329 #define CSR_VSTOPEI 0x25c

330 #define CSR_VSTOPI 0xeb0

331

332 /* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */

333 #define CSR_HIDELEGH 0x613

334 #define CSR_HVIENH 0x618

335 #define CSR_HVIPH 0x655

336 #define CSR_HVIPRIO1H 0x656

337 #define CSR_HVIPRIO2H 0x657

338 #define CSR_VSIEH 0x214

339 #define CSR_VSIPH 0x254

340

341 #define CSR_MSTATUS 0x300

342 #define CSR_MISA 0x301

343 #define CSR_MIDELEG 0x303

344 #define CSR_MIE 0x304

345 #define CSR_MTVEC 0x305

346 #define CSR_MENVCFG 0x30a

347 #define CSR_MENVCFGH 0x31a

348 #define CSR_MSCRATCH 0x340

349 #define CSR_MEPC 0x341

350 #define CSR_MCAUSE 0x342

351 #define CSR_MTVAL 0x343

352 #define CSR_MIP 0x344

353 #define CSR_PMPCFG0 0x3a0

354 #define CSR_PMPADDR0 0x3b0

355 #define CSR_MVENDORID 0xf11

356 #define CSR_MARCHID 0xf12

357 #define CSR_MIMPID 0xf13

358 #define CSR_MHARTID 0xf14

359

360 /* Machine-Level Window to Indirectly Accessed Registers (AIA) */

361 #define CSR_MISELECT 0x350

362 #define CSR_MIREG 0x351

363

364 /* Machine-Level Interrupts (AIA) */

365 #define CSR_MTOPEI 0x35c

366 #define CSR_MTOPI 0xfb0

367

368 /* Virtual Interrupts for Supervisor Level (AIA) */

369 #define CSR_MVIEN 0x308

370 #define CSR_MVIP 0x309

371

372 /* Machine-Level High-Half CSRs (AIA) */

373 #define CSR_MIDELEGH 0x313

374 #define CSR_MIEH 0x314

375 #define CSR_MVIENH 0x318

376 #define CSR_MVIPH 0x319

377 #define CSR_MIPH 0x354

378

379 #ifdef CONFIG_RISCV_M_MODE

380 # define CSR_STATUS CSR_MSTATUS

381 # define CSR_IE CSR_MIE

382 # define CSR_TVEC CSR_MTVEC

383 # define CSR_SCRATCH CSR_MSCRATCH

384 # define CSR_EPC CSR_MEPC

385 # define CSR_CAUSE CSR_MCAUSE

386 # define CSR_TVAL CSR_MTVAL

387 # define CSR_IP CSR_MIP

388

389 # define CSR_IEH CSR_MIEH

390 # define CSR_ISELECT CSR_MISELECT

391 # define CSR_IREG CSR_MIREG

392 # define CSR_IPH CSR_MIPH

393 # define CSR_TOPEI CSR_MTOPEI

394 # define CSR_TOPI CSR_MTOPI

395

396 # define SR_IE SR_MIE

397 # define SR_PIE SR_MPIE

398 # define SR_PP SR_MPP

399

400 # define RV_IRQ_SOFT IRQ_M_SOFT

401 # define RV_IRQ_TIMER IRQ_M_TIMER

402 # define RV_IRQ_EXT IRQ_M_EXT

403 #else /* CONFIG_RISCV_M_MODE */

404 # define CSR_STATUS CSR_SSTATUS

405 # define CSR_IE CSR_SIE

406 # define CSR_TVEC CSR_STVEC

407 # define CSR_SCRATCH CSR_SSCRATCH

408 # define CSR_EPC CSR_SEPC

409 # define CSR_CAUSE CSR_SCAUSE

410 # define CSR_TVAL CSR_STVAL

411 # define CSR_IP CSR_SIP

412

413 # define CSR_IEH CSR_SIEH

414 # define CSR_ISELECT CSR_SISELECT

415 # define CSR_IREG CSR_SIREG

416 # define CSR_IPH CSR_SIPH

417 # define CSR_TOPEI CSR_STOPEI

418 # define CSR_TOPI CSR_STOPI

419

420 # define SR_IE SR_SIE

421 # define SR_PIE SR_SPIE

422 # define SR_PP SR_SPP

423

424 # define RV_IRQ_SOFT IRQ_S_SOFT

425 # define RV_IRQ_TIMER IRQ_S_TIMER

426 # define RV_IRQ_EXT IRQ_S_EXT

427 # define RV_IRQ_PMU IRQ_PMU_OVF

428 # define SIP_LCOFIP (_AC(0x1, UL) << IRQ_PMU_OVF)

429

430 #endif /* !CONFIG_RISCV_M_MODE */

431

432 /* IE/IP (Supervisor/Machine Interrupt Enable/Pending) flags */

433 #define IE_SIE (_AC(0x1, UL) << RV_IRQ_SOFT)

434 #define IE_TIE (_AC(0x1, UL) << RV_IRQ_TIMER)

435 #define IE_EIE (_AC(0x1, UL) << RV_IRQ_EXT)

436

437 #ifndef __ASSEMBLY__

438

439 #define csr_swap(csr, val) \

440 ({ \

441 unsigned long __v = (unsigned long)(val); \

442 __asm__ __volatile__ ("csrrw %0, " __ASM_STR(csr) ", %1"\

443 : "=r" (__v) : "rK" (__v) \

444 : "memory"); \

445 __v; \

446 })

447

448 #define csr_read(csr) \

449 ({ \

450 register unsigned long __v; \

451 __asm__ __volatile__ ("csrr %0, " __ASM_STR(csr) \

452 : "=r" (__v) : \

453 : "memory"); \

454 __v; \

455 })

456

457 #define csr_write(csr, val) \

458 ({ \

459 unsigned long __v = (unsigned long)(val); \

460 __asm__ __volatile__ ("csrw " __ASM_STR(csr) ", %0" \

461 : : "rK" (__v) \

462 : "memory"); \

463 })

464

465 #define csr_read_set(csr, val) \

466 ({ \

467 unsigned long __v = (unsigned long)(val); \

468 __asm__ __volatile__ ("csrrs %0, " __ASM_STR(csr) ", %1"\

469 : "=r" (__v) : "rK" (__v) \

470 : "memory"); \

471 __v; \

472 })

473

474 #define csr_set(csr, val) \

475 ({ \

476 unsigned long __v = (unsigned long)(val); \

477 __asm__ __volatile__ ("csrs " __ASM_STR(csr) ", %0" \

478 : : "rK" (__v) \

479 : "memory"); \

480 })

481

482 #define csr_read_clear(csr, val) \

483 ({ \

484 unsigned long __v = (unsigned long)(val); \

485 __asm__ __volatile__ ("csrrc %0, " __ASM_STR(csr) ", %1"\

486 : "=r" (__v) : "rK" (__v) \

487 : "memory"); \

488 __v; \

489 })

490

491 #define csr_clear(csr, val) \

492 ({ \

493 unsigned long __v = (unsigned long)(val); \

494 __asm__ __volatile__ ("csrc " __ASM_STR(csr) ", %0" \

495 : : "rK" (__v) \

496 : "memory"); \

497 })

498

499 #endif /* __ASSEMBLY__ */

500

501 #endif /* _ASM_RISCV_CSR_H */