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(parent: 19ab69a) | patch
cxl/port: Store the downstream port's Component Register mappings in struct cxl_dport
authorRobert Richter <rrichter@amd.com>
Thu, 22 Jun 2023 20:55:11 +0000 (15:55 -0500)
committerDan Williams <dan.j.williams@intel.com>
Sun, 25 Jun 2023 19:22:53 +0000 (12:22 -0700)
commit5d2ffbe4b81a3b6353bf888a523e7e5d4fec47ad
tree536b1713da2cbbd90882e2d75a93de5cb97fda0ctree | snapshot
parent19ab69a60e3ba58b4942b9ab5095cf90477a54cecommit | diff
cxl/port: Store the downstream port's Component Register mappings in struct cxl_dport

Same as for ports, also store the downstream port's Component Register
mappings, use struct cxl_dport for that.

Signed-off-by: Robert Richter <rrichter@amd.com>
Signed-off-by: Terry Bowman <terry.bowman@amd.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Link: https://lore.kernel.org/r/20230622205523.85375-16-terry.bowman@amd.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
drivers/cxl/core/port.c diff | blob | history
drivers/cxl/cxl.h diff | blob | history
ep93xx device tree rework repo: git://git.maquefel.me/linux.git