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i2c: piix4: Enable EFCH MMIO for Family 17h+
authorTerry Bowman <terry.bowman@amd.com>
Wed, 9 Feb 2022 17:27:17 +0000 (11:27 -0600)
committerWolfram Sang <wsa@kernel.org>
Fri, 11 Feb 2022 14:38:23 +0000 (15:38 +0100)
commit6cf72f41808ab5db1d7718b999b3ff0166e67e45
treeb796a0e0bc0b83c30616562814200e58a4782727tree | snapshot
parent381a3083c6747ae5cdbef9b176d57d1b966db49fcommit | diff
i2c: piix4: Enable EFCH MMIO for Family 17h+

Enable EFCH MMIO using check for SMBus PCI revision ID value 0x51 or
greater. This PCI revision ID check will enable family 17h and future
AMD processors with the same EFCH SMBus controller HW.

Signed-off-by: Terry Bowman <terry.bowman@amd.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Reviewed-by: Jean Delvare <jdelvare@suse.de>
Signed-off-by: Wolfram Sang <wsa@kernel.org>
drivers/i2c/busses/i2c-piix4.c diff | blob | history
ep93xx device tree rework repo: git://git.maquefel.me/linux.git