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(parent: 940b309) | patch
configure: Merge riscv32 and riscv64 host architectures
authorRichard Henderson <richard.henderson@linaro.org>
Fri, 17 Sep 2021 18:08:09 +0000 (11:08 -0700)
committerRichard Henderson <richard.henderson@linaro.org>
Sat, 30 Oct 2021 16:52:04 +0000 (09:52 -0700)
commitba0e73336200a04f797ae0c13922146a135cb118
tree09a3dd7150c4746ba5af15dc173e627d81de4d90tree | snapshot
parent940b30904e928854250988c3802f334c8ee12bd4commit | diff
configure: Merge riscv32 and riscv64 host architectures

The existing code for safe-syscall.inc.S will compile
without change for riscv32 and riscv64.  We may also
drop the meson.build stanza that merges them for tcg/.

Reviewed-by: Warner Losh <imp@bsdimp.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
configure diff | blob | history
linux-user/host/riscv/hostdep.h [new file with mode: 0644] blob
linux-user/host/riscv/safe-syscall.inc.S [new file with mode: 0644] blob
linux-user/host/riscv32/hostdep.h [deleted file] blob | history
linux-user/host/riscv64/hostdep.h [deleted file] blob | history
linux-user/host/riscv64/safe-syscall.inc.S [deleted file] blob | history
meson.build diff | blob | history
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