From 010ce438e7bba81ae1b525795ec2f5313d78485a Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 17 Nov 2020 10:03:27 +0100 Subject: [PATCH] clk: renesas: r8a779a0: Add MSIOF clocks Add the module clocks used by the Clock-Synchronized Serial Interface with FIFO (MSIOF) instances on the Renesas R-Car V3U (r8a779a0) SoC. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20201117090329.2128904-3-geert+renesas@glider.be --- drivers/clk/renesas/r8a779a0-cpg-mssr.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/clk/renesas/r8a779a0-cpg-mssr.c b/drivers/clk/renesas/r8a779a0-cpg-mssr.c index 1f4147254a467..067c71067fd48 100644 --- a/drivers/clk/renesas/r8a779a0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a779a0-cpg-mssr.c @@ -158,6 +158,12 @@ static const struct mssr_mod_clk r8a779a0_mod_clks[] __initconst = { DEF_MOD("hscif1", 515, R8A779A0_CLK_S1D2), DEF_MOD("hscif2", 516, R8A779A0_CLK_S1D2), DEF_MOD("hscif3", 517, R8A779A0_CLK_S1D2), + DEF_MOD("msi0", 618, R8A779A0_CLK_MSO), + DEF_MOD("msi1", 619, R8A779A0_CLK_MSO), + DEF_MOD("msi2", 620, R8A779A0_CLK_MSO), + DEF_MOD("msi3", 621, R8A779A0_CLK_MSO), + DEF_MOD("msi4", 622, R8A779A0_CLK_MSO), + DEF_MOD("msi5", 623, R8A779A0_CLK_MSO), DEF_MOD("scif0", 702, R8A779A0_CLK_S1D8), DEF_MOD("scif1", 703, R8A779A0_CLK_S1D8), DEF_MOD("scif3", 704, R8A779A0_CLK_S1D8), -- 2.30.2