From 01198add29ddecc1283f1ab5cb4b34885e7daaa3 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Mon, 11 Nov 2024 17:15:56 +0100 Subject: [PATCH] hw/net/xilinx_ethlite: Map TX_GIE as MMIO MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Add TX_GIE to the TX registers MMIO region. Before TX_GIE1 was accessed as RAM, with no effect. Now it is accessed as MMIO, also without any effect. The memory flat view becomes: (qemu) info mtree -f FlatView #0 Root memory region: system 0000000081000000-00000000810007e3 (prio 0, i/o): xlnx.xps-ethernetlite 00000000810007e4-00000000810007f3 (prio 0, i/o): ethlite.mdio 00000000810007f4-00000000810007fb (prio 0, i/o): ethlite.tx[0]io 00000000810007fc-0000000081000ff3 (prio 0, i/o): xlnx.xps-ethernetlite @00000000000007fc 0000000081000ff4-0000000081000ffb (prio 0, i/o): ethlite.tx[1]io 0000000081000ffc-00000000810017fb (prio 0, i/o): xlnx.xps-ethernetlite @0000000000000ffc 00000000810017fc-00000000810017ff (prio 0, i/o): ethlite.rx[0]io 0000000081001800-0000000081001ffb (prio 0, i/o): xlnx.xps-ethernetlite @0000000000001800 0000000081001ffc-0000000081001fff (prio 0, i/o): ethlite.rx[1]io Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Edgar E. Iglesias Message-Id: <20241112181044.92193-18-philmd@linaro.org> --- hw/net/xilinx_ethlite.c | 17 +++++++---------- 1 file changed, 7 insertions(+), 10 deletions(-) diff --git a/hw/net/xilinx_ethlite.c b/hw/net/xilinx_ethlite.c index 5dac44fa68..898c09b398 100644 --- a/hw/net/xilinx_ethlite.c +++ b/hw/net/xilinx_ethlite.c @@ -42,7 +42,6 @@ #define BUFSZ_MAX 0x07e4 #define A_MDIO_BASE 0x07e4 #define A_TX_BASE0 0x07f4 -#define R_TX_GIE0 (0x07f8 / 4) #define R_TX_CTRL0 (0x07fc / 4) #define R_TX_BUF1 (0x0800 / 4) #define A_TX_BASE1 0x0ff4 @@ -56,6 +55,7 @@ enum { TX_LEN = 0, + TX_GIE = 1, TX_MAX }; @@ -141,6 +141,9 @@ static uint64_t port_tx_read(void *opaque, hwaddr addr, unsigned int size) case TX_LEN: r = s->port[port_index].reg.tx_len; break; + case TX_GIE: + r = s->port[port_index].reg.tx_gie; + break; default: g_assert_not_reached(); } @@ -158,6 +161,9 @@ static void port_tx_write(void *opaque, hwaddr addr, uint64_t value, case TX_LEN: s->port[port_index].reg.tx_len = value; break; + case TX_GIE: + s->port[port_index].reg.tx_gie = value; + break; default: g_assert_not_reached(); } @@ -237,10 +243,6 @@ eth_read(void *opaque, hwaddr addr, unsigned int size) switch (addr) { - case R_TX_GIE0: - r = s->port[port_index].reg.tx_gie; - break; - case R_TX_CTRL1: case R_TX_CTRL0: r = s->port[port_index].reg.tx_ctrl; @@ -285,11 +287,6 @@ eth_write(void *opaque, hwaddr addr, s->port[port_index].reg.tx_ctrl = value & ~(CTRL_P | CTRL_S); break; - /* Keep these native. */ - case R_TX_GIE0: - s->port[port_index].reg.tx_gie = value; - break; - default: s->regs[addr] = tswap32(value); break; -- 2.30.2