From 01b8f5b53e4df5d22d0e273fea5124a972e8d5c4 Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Wed, 25 Nov 2020 08:19:18 +0100 Subject: [PATCH] dt-bindings: reset: ocelot: Add Luton and Jaguar2 support This adds the support for 2 others MIPS based VCore III SoCs: Luton and Jaguar2. Signed-off-by: Gregory CLEMENT Signed-off-by: Sebastian Reichel --- .../devicetree/bindings/power/reset/ocelot-reset.txt | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt b/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt index 4d530d8154848..c5de7b555feb9 100644 --- a/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt +++ b/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt @@ -7,7 +7,9 @@ The reset registers are both present in the MSCC vcoreiii MIPS and microchip Sparx5 armv8 SoC's. Required Properties: - - compatible: "mscc,ocelot-chip-reset" or "microchip,sparx5-chip-reset" + + - compatible: "mscc,ocelot-chip-reset", "mscc,luton-chip-reset", + "mscc,jaguar2-chip-reset" or "microchip,sparx5-chip-reset" Example: reset@1070008 { -- 2.30.2