From 06279f82da68882b83524385834eeacf1993724f Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 8 Jun 2022 17:17:42 +0200 Subject: [PATCH] arm64: dts: renesas: r8a779a0: Add CPU0 core clock Describe the clock for the first Cortex-A76 CPU core. For now no operating points are defined. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/3ace4eea4ff1cdc0f7b8ea7d0433c1063d795785.1654701400.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r8a779a0.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi index 8162ef8503761..3d668709d8a8d 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi @@ -41,6 +41,7 @@ device_type = "cpu"; power-domains = <&sysc R8A779A0_PD_A1E0D0C0>; next-level-cache = <&L3_CA76_0>; + clocks = <&cpg CPG_CORE R8A779A0_CLK_Z0>; }; L3_CA76_0: cache-controller-0 { -- 2.30.2