From 06bfc045d54cd7cb769aab5af45f6022c2ce77a7 Mon Sep 17 00:00:00 2001 From: Eric Huang Date: Sat, 27 Feb 2021 16:51:19 -0500 Subject: [PATCH] drm/amdgpu: set CPU mapping of vram as cached for A+A mode MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit New A+A HW supports cached vram mapped to cpu. Signed-off-by: Eric Huang Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 0ea1b68e7bb9f..c5fea144b759d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -673,7 +673,10 @@ static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_reso mem->bus.offset += adev->gmc.aper_base; mem->bus.is_iomem = true; - mem->bus.caching = ttm_write_combined; + if (adev->gmc.xgmi.connected_to_cpu) + mem->bus.caching = ttm_cached; + else + mem->bus.caching = ttm_write_combined; break; default: return -EINVAL; -- 2.30.2