From 1625fbc1f73f1fa8f77c38ea554cc0b2327b156b Mon Sep 17 00:00:00 2001 From: Biju Das Date: Mon, 19 Sep 2022 09:41:10 +0100 Subject: [PATCH] clk: renesas: rzg2l: Support sd clk mux round operation Currently, determine_rate() is not doing any round operation and due to this it always selects a lower clock source compared to the closest higher one. Support sd clk mux round operation by passing CLK_MUX_ROUND_CLOSEST flag to clk_mux_determine_rate_flags(). Signed-off-by: Biju Das Link: https://lore.kernel.org/r/20220919084110.3065156-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/clk/renesas/rzg2l-cpg.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c index 3ff6ecd617565..5dfe3624f6812 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -182,7 +182,7 @@ rzg2l_cpg_mux_clk_register(const struct cpg_core_clk *core, static int rzg2l_cpg_sd_clk_mux_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) { - return clk_mux_determine_rate_flags(hw, req, 0); + return clk_mux_determine_rate_flags(hw, req, CLK_MUX_ROUND_CLOSEST); } static int rzg2l_cpg_sd_clk_mux_set_parent(struct clk_hw *hw, u8 index) -- 2.30.2