From 1e9ae61d172f92863c84e5745cc59d485f92bdea Mon Sep 17 00:00:00 2001 From: =?utf8?q?Ville=20Syrj=C3=A4l=C3=A4?= Date: Thu, 30 Sep 2021 16:43:07 +0300 Subject: [PATCH] drm/i915: Clear leftover DP vswing/preemphasis values before modeset MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Currently we clear the leftover vswing/preemphasis values only at the start of link training. That means the initial vswing programming performed during modeset is going to use stale values left over from the previous link training sequence, and then at the start of link training we're going to reset the levels back to 0. Seems much better to make sure we start with level 0 from the get go. Additionally if LTTPRs are present the leftover vswing/preemphasis values are those of the last link in the chain, so not the values that our PHY is even using after a successful link training sequence. So let's make sure everything is cleared up before we start programming anything. Suggested-by: Imre Deak Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20210930134310.31669-1-ville.syrjala@linux.intel.com Reviewed-by: Imre Deak --- drivers/gpu/drm/i915/display/intel_dp.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 8f5a935b72b6c..74a657ae131a3 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -1835,6 +1835,7 @@ intel_dp_compute_config(struct intel_encoder *encoder, void intel_dp_set_link_params(struct intel_dp *intel_dp, int link_rate, int lane_count) { + memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set)); intel_dp->link_trained = false; intel_dp->link_rate = link_rate; intel_dp->lane_count = lane_count; -- 2.30.2