From 1f5d9cad08b710d03a7061285bf654c3582e9cb2 Mon Sep 17 00:00:00 2001 From: Likun Gao Date: Wed, 4 Mar 2020 16:40:24 +0800 Subject: [PATCH] drm/amdgpu: fix SDMA hdp flush engine conflict MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Each of HDP flush engine should be used by one ring, correct allocate of hdp flush engine to SDMA ring. Correct me value of each SDMA ring, as it was cleared when init microcode. Reviewed-by: Christian König Signed-off-by: Likun Gao Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c index 52206050adb91..f072cef28b603 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c @@ -391,10 +391,7 @@ static void sdma_v5_2_ring_emit_hdp_flush(struct amdgpu_ring *ring) u32 ref_and_mask = 0; const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; - if (ring->me == 0) - ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0; - else - ref_and_mask = nbio_hf_reg->ref_and_mask_sdma1; + ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me; amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) | @@ -1224,6 +1221,7 @@ static int sdma_v5_2_sw_init(void *handle) ring = &adev->sdma.instance[i].ring; ring->ring_obj = NULL; ring->use_doorbell = true; + ring->me = i; DRM_INFO("use_doorbell being set to: [%s]\n", ring->use_doorbell?"true":"false"); -- 2.30.2