From 25ea3411bd23c5f0043881e2c6710423eb411784 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Ville=20Syrj=C3=A4l=C3=A4?= Date: Tue, 6 Jun 2023 22:14:58 +0300 Subject: [PATCH] drm/i915/dsb: Use non-posted register writes for legacy LUT MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit The DSB has problems writing the legacy LUT. The two workarounds I've discoverted are: - write each entry twice back to back - use non-posted writes Let's use non-posted writes as that seems a bit more standard. TODO: measure which is faster Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20230606191504.18099-14-ville.syrjala@linux.intel.com Reviewed-by: Uma Shankar --- drivers/gpu/drm/i915/display/intel_color.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index 7da79ffeb77bf..9f80228f96cb7 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -1329,9 +1329,20 @@ static void ilk_load_lut_8(const struct intel_crtc_state *crtc_state, lut = blob->data; + /* + * DSB fails to correctly load the legacy LUT + * unless we either write each entry twice, + * or use non-posted writes + */ + if (crtc_state->dsb) + intel_dsb_nonpost_start(crtc_state->dsb); + for (i = 0; i < 256; i++) ilk_lut_write(crtc_state, LGC_PALETTE(pipe, i), i9xx_lut_8(&lut[i])); + + if (crtc_state->dsb) + intel_dsb_nonpost_end(crtc_state->dsb); } static void ilk_load_lut_10(const struct intel_crtc_state *crtc_state, -- 2.30.2