From 26c5d372e4848cbe85bcda10a4c5e98ad3aa051a Mon Sep 17 00:00:00 2001
From: Aurelien Jarno <aurelien@aurel32.net>
Date: Sat, 20 Mar 2010 12:10:20 +0100
Subject: [PATCH] tcg/arm: fix load/store definitions for 32-bit targets
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
---
tcg/arm/tcg-target.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c
index 35e14c1938..b50bb762a6 100644
--- a/tcg/arm/tcg-target.c
+++ b/tcg/arm/tcg-target.c
@@ -1580,6 +1580,19 @@ static const TCGTargetOpDef arm_op_defs[] = {
{ INDEX_op_brcond2_i32, { "r", "r", "r", "r" } },
{ INDEX_op_setcond2_i32, { "r", "r", "r", "r", "r" } },
+#if TARGET_LONG_BITS == 32
+ { INDEX_op_qemu_ld8u, { "r", "x" } },
+ { INDEX_op_qemu_ld8s, { "r", "x" } },
+ { INDEX_op_qemu_ld16u, { "r", "x" } },
+ { INDEX_op_qemu_ld16s, { "r", "x" } },
+ { INDEX_op_qemu_ld32u, { "r", "x" } },
+ { INDEX_op_qemu_ld64, { "d", "r", "x" } },
+
+ { INDEX_op_qemu_st8, { "x", "x" } },
+ { INDEX_op_qemu_st16, { "x", "x" } },
+ { INDEX_op_qemu_st32, { "x", "x" } },
+ { INDEX_op_qemu_st64, { "x", "D", "x" } },
+#else
{ INDEX_op_qemu_ld8u, { "r", "x", "X" } },
{ INDEX_op_qemu_ld8s, { "r", "x", "X" } },
{ INDEX_op_qemu_ld16u, { "r", "x", "X" } },
@@ -1591,6 +1604,7 @@ static const TCGTargetOpDef arm_op_defs[] = {
{ INDEX_op_qemu_st16, { "x", "x", "X" } },
{ INDEX_op_qemu_st32, { "x", "x", "X" } },
{ INDEX_op_qemu_st64, { "x", "D", "x", "X" } },
+#endif
{ INDEX_op_ext8s_i32, { "r", "r" } },
{ INDEX_op_ext16s_i32, { "r", "r" } },
--
2.30.2