From 29a5f5f0b08af1bac5c3d2c0948ed7f56ba4d255 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Fri, 29 Apr 2022 09:57:36 +0300 Subject: [PATCH] ARM: dts: Group omap3 CM_CLKSEL1_EMU clocks The clksel related registers on omap3 cause unique_unit_address and node_name_chars_strict warnings with the W=1 or W=2 make flags enabled. With the clock drivers updated, we can now avoid most of these warnings by grouping the TI component clocks using the TI clksel binding, and with the use of clock-output-names property to avoid non-standard node names for the clocks. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap3xxx-clocks.dtsi | 152 +++++++++++++------------ 1 file changed, 80 insertions(+), 72 deletions(-) diff --git a/arch/arm/boot/dts/omap3xxx-clocks.dtsi b/arch/arm/boot/dts/omap3xxx-clocks.dtsi index 8a16e49fdf246..2e13ca11ceeaf 100644 --- a/arch/arm/boot/dts/omap3xxx-clocks.dtsi +++ b/arch/arm/boot/dts/omap3xxx-clocks.dtsi @@ -254,14 +254,87 @@ reg = <0x0d00>, <0x0d20>, <0x0d40>, <0x0d30>; }; - dpll3_m3_ck: dpll3_m3_ck@1140 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll3_ck>; - ti,bit-shift = <16>; - ti,max-div = <31>; + /* CM_CLKSEL1_EMU */ + clock@1140 { + compatible = "ti,clksel"; reg = <0x1140>; - ti,index-starts-at-one; + #clock-cells = <2>; + #address-cells = <0>; + + dpll3_m3_ck: clock-dpll3-m3 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll3_m3_ck"; + clocks = <&dpll3_ck>; + ti,bit-shift = <16>; + ti,max-div = <31>; + ti,index-starts-at-one; + }; + + dpll4_m6_ck: clock-dpll4-m6 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll4_m6_ck"; + clocks = <&dpll4_ck>; + ti,bit-shift = <24>; + ti,max-div = <63>; + ti,index-starts-at-one; + }; + + emu_src_mux_ck: clock-emu-src-mux { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "emu_src_mux_ck"; + clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>; + }; + + pclk_fck: clock-pclk-fck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "pclk_fck"; + clocks = <&emu_src_ck>; + ti,bit-shift = <8>; + ti,max-div = <7>; + ti,index-starts-at-one; + }; + + pclkx2_fck: clock-pclkx2-fck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "pclkx2_fck"; + clocks = <&emu_src_ck>; + ti,bit-shift = <6>; + ti,max-div = <3>; + ti,index-starts-at-one; + }; + + atclk_fck: clock-atclk-fck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "atclk_fck"; + clocks = <&emu_src_ck>; + ti,bit-shift = <4>; + ti,max-div = <3>; + ti,index-starts-at-one; + }; + + traceclk_src_fck: clock-traceclk-src-fck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "traceclk_src_fck"; + clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>; + ti,bit-shift = <2>; + }; + + traceclk_fck: clock-traceclk-fck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "traceclk_fck"; + clocks = <&traceclk_src_fck>; + ti,bit-shift = <11>; + ti,max-div = <7>; + ti,index-starts-at-one; + }; }; dpll3_m3x2_mul_ck: dpll3_m3x2_mul_ck { @@ -500,16 +573,6 @@ ti,set-rate-parent; }; - dpll4_m6_ck: dpll4_m6_ck@1140 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll4_ck>; - ti,bit-shift = <24>; - ti,max-div = <63>; - reg = <0x1140>; - ti,index-starts-at-one; - }; - dpll4_m6x2_mul_ck: dpll4_m6x2_mul_ck { #clock-cells = <0>; compatible = "fixed-factor-clock"; @@ -1633,67 +1696,12 @@ }; }; - emu_src_mux_ck: emu_src_mux_ck@1140 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>; - reg = <0x1140>; - }; - emu_src_ck: emu_src_ck { #clock-cells = <0>; compatible = "ti,clkdm-gate-clock"; clocks = <&emu_src_mux_ck>; }; - pclk_fck: pclk_fck@1140 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&emu_src_ck>; - ti,bit-shift = <8>; - ti,max-div = <7>; - reg = <0x1140>; - ti,index-starts-at-one; - }; - - pclkx2_fck: pclkx2_fck@1140 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&emu_src_ck>; - ti,bit-shift = <6>; - ti,max-div = <3>; - reg = <0x1140>; - ti,index-starts-at-one; - }; - - atclk_fck: atclk_fck@1140 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&emu_src_ck>; - ti,bit-shift = <4>; - ti,max-div = <3>; - reg = <0x1140>; - ti,index-starts-at-one; - }; - - traceclk_src_fck: traceclk_src_fck@1140 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>; - ti,bit-shift = <2>; - reg = <0x1140>; - }; - - traceclk_fck: traceclk_fck@1140 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&traceclk_src_fck>; - ti,bit-shift = <11>; - ti,max-div = <7>; - reg = <0x1140>; - ti,index-starts-at-one; - }; - secure_32k_fck: secure_32k_fck { #clock-cells = <0>; compatible = "fixed-clock"; -- 2.30.2