From 2a764b7c708a796e6b45c39f12b962371278ca05 Mon Sep 17 00:00:00 2001 From: Vandita Kulkarni Date: Wed, 15 Sep 2021 11:13:38 +0530 Subject: [PATCH] drm/i915/display: Fix the dsc check while selecting min_cdclk The right parameter that selects second dsc engine is dsc_split. Hence use dsc_split instead of slice_count while selecting the cdclk in order to accommodate 1ppc limitaion of vdsc. Fixes: fe01883fdcef ("drm/i915: Get proper min cdclk if vDSC enabled") Suggested-by: Jani Nikula Signed-off-by: Vandita Kulkarni Reviewed-by: Jani Nikula Signed-off-by: Uma Shankar Link: https://patchwork.freedesktop.org/patch/msgid/20210915054338.29869-1-vandita.kulkarni@intel.com --- drivers/gpu/drm/i915/display/intel_cdclk.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index 9aec17b33819e..3a1cdb3937aac 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -2140,13 +2140,11 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state) min_cdclk = max(intel_planes_min_cdclk(crtc_state), min_cdclk); /* - * VDSC engine can process only 1 pixel per Cd clock. - * In case VDSC is used and max slice count == 1, - * max supported pixel clock should be 100% of CD clock. - * Then do min_cdclk and pixel clock comparison to get cdclk. + * When we decide to use only one VDSC engine, since + * each VDSC operates with 1 ppc throughput, pixel clock + * cannot be higher than the VDSC clock (cdclk) */ - if (crtc_state->dsc.compression_enable && - crtc_state->dsc.slice_count == 1) + if (crtc_state->dsc.compression_enable && !crtc_state->dsc.dsc_split) min_cdclk = max(min_cdclk, (int)crtc_state->pixel_rate); /* -- 2.30.2