From 2e86e6300c4a98b1d0c93e03c491b0fd5d552eb5 Mon Sep 17 00:00:00 2001 From: Rajendra Nayak <quic_rjendra@quicinc.com> Date: Tue, 5 Dec 2023 11:54:03 +0530 Subject: [PATCH] arm64: defconfig: Enable X1E80100 SoC base configs Enable GCC, Pinctrl and Interconnect configs for Qualcomm's X1E80100 SoC which is required to boot X1E80100 QCP/CRD boards to a console shell. The configs are required to be marked as builtin and not modules due to the console driver dependencies. Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com> Co-developed-by: Sibi Sankar <quic_sibis@quicinc.com> Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20231205062403.14848-6-quic_sibis@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org> --- arch/arm64/configs/defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 6df3196acd5c7..04f3f0e59a5c2 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -619,6 +619,7 @@ CONFIG_PINCTRL_SC8280XP_LPASS_LPI=m CONFIG_PINCTRL_SM8550=y CONFIG_PINCTRL_SM8650=y CONFIG_PINCTRL_SM8550_LPASS_LPI=m +CONFIG_PINCTRL_X1E80100=y CONFIG_PINCTRL_LPASS_LPI=m CONFIG_GPIO_AGGREGATOR=m CONFIG_GPIO_ALTERA=m @@ -1224,6 +1225,7 @@ CONFIG_COMMON_CLK_MT8192_SCP_ADSP=y CONFIG_COMMON_CLK_MT8192_VDECSYS=y CONFIG_COMMON_CLK_MT8192_VENCSYS=y CONFIG_COMMON_CLK_QCOM=y +CONFIG_CLK_X1E80100_GCC=y CONFIG_QCOM_A53PLL=y CONFIG_QCOM_CLK_APCS_MSM8916=y CONFIG_QCOM_CLK_APCC_MSM8996=y @@ -1540,6 +1542,7 @@ CONFIG_INTERCONNECT_QCOM_SM8350=m CONFIG_INTERCONNECT_QCOM_SM8450=y CONFIG_INTERCONNECT_QCOM_SM8550=y CONFIG_INTERCONNECT_QCOM_SM8650=y +CONFIG_INTERCONNECT_QCOM_X1E80100=y CONFIG_COUNTER=m CONFIG_RZ_MTU3_CNT=m CONFIG_HTE=y -- 2.30.2