From 31e7aa7ed7393af6cb92a6c569738d4d50d7f6fc Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Sun, 7 Feb 2021 12:51:38 -0600 Subject: [PATCH] dt-bindings: clk: versaclock5: Add optional load capacitance property There are two registers which can set the load capacitance for XTAL1 and XTAL2. These are optional registers when using an external crystal. Since XTAL1 and XTAL2 will set to the same value, update the binding to support a single property called xtal-load-femtofarads. Signed-off-by: Adam Ford Link: https://lore.kernel.org/r/20210207185140.3653350-1-aford173@gmail.com Reviewed-by: Rob Herring Signed-off-by: Stephen Boyd --- .../devicetree/bindings/clock/idt,versaclock5.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/idt,versaclock5.yaml b/Documentation/devicetree/bindings/clock/idt,versaclock5.yaml index 2ac1131fd9222..c268debe5b8d5 100644 --- a/Documentation/devicetree/bindings/clock/idt,versaclock5.yaml +++ b/Documentation/devicetree/bindings/clock/idt,versaclock5.yaml @@ -59,6 +59,12 @@ properties: minItems: 1 maxItems: 2 + idt,xtal-load-femtofarads: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 9000 + maximum: 22760 + description: Optional load capacitor for XTAL1 and XTAL2 + patternProperties: "^OUT[1-4]$": type: object -- 2.30.2