From 33e3b0eb755074a870fd926ebd84de52e7302090 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Ilpo=20J=C3=A4rvinen?= Date: Thu, 11 May 2023 15:10:28 +0300 Subject: [PATCH] serial: 8250_rt288x: Name non-standard divisor latch reg MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Instead of a literal, add proper name for the non-standard divisor latch register. Signed-off-by: Ilpo Järvinen Link: https://lore.kernel.org/r/20230511121029.13128-6-ilpo.jarvinen@linux.intel.com Signed-off-by: Greg Kroah-Hartman --- drivers/tty/serial/8250/8250_rt288x.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/tty/serial/8250/8250_rt288x.c b/drivers/tty/serial/8250/8250_rt288x.c index 51b1cf5476dd5..b091a1269bfaa 100644 --- a/drivers/tty/serial/8250/8250_rt288x.c +++ b/drivers/tty/serial/8250/8250_rt288x.c @@ -12,6 +12,8 @@ #include "8250.h" +#define RT288X_DL 0x28 + #define UART_REG_UNMAPPED -1 /* Au1x00/RT288x UART hardware has a weird register layout */ @@ -60,12 +62,12 @@ static void au_serial_out(struct uart_port *p, int offset, int value) /* Au1x00 haven't got a standard divisor latch */ static u32 au_serial_dl_read(struct uart_8250_port *up) { - return __raw_readl(up->port.membase + 0x28); + return __raw_readl(up->port.membase + RT288X_DL); } static void au_serial_dl_write(struct uart_8250_port *up, u32 value) { - __raw_writel(value, up->port.membase + 0x28); + __raw_writel(value, up->port.membase + RT288X_DL); } int au_platform_setup(struct plat_serial8250_port *p) -- 2.30.2