From 39409aa4244f22eae3fa8f8db4b0cf9466b73c44 Mon Sep 17 00:00:00 2001
From: Thierry Reding <thierry.reding@gmail.com>
Date: Mon, 18 Nov 2013 16:11:36 +0100
Subject: [PATCH] clk: tegra: Initialize DSI low-power clocks

The low-power DSI clocks are used during host-driven transactions on the
DSI bus. Documentation recommends that they be children of PLLP and run
at a frequency of at least 52 MHz.

Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 drivers/clk/tegra/clk-tegra114.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
index 2a1b0b82462a1..29b912582e3d5 100644
--- a/drivers/clk/tegra/clk-tegra114.c
+++ b/drivers/clk/tegra/clk-tegra114.c
@@ -1299,6 +1299,8 @@ static struct tegra_clk_init_table init_table[] __initdata = {
 	{TEGRA114_CLK_DISP2, TEGRA114_CLK_PLL_P, 0, 0},
 	{TEGRA114_CLK_GR2D, TEGRA114_CLK_PLL_C2, 300000000, 0},
 	{TEGRA114_CLK_GR3D, TEGRA114_CLK_PLL_C2, 300000000, 0},
+	{TEGRA114_CLK_DSIALP, TEGRA114_CLK_PLL_P, 68000000, 0},
+	{TEGRA114_CLK_DSIBLP, TEGRA114_CLK_PLL_P, 68000000, 0},
 
 	/* This MUST be the last entry. */
 	{TEGRA114_CLK_CLK_MAX, TEGRA114_CLK_CLK_MAX, 0, 0},
-- 
2.30.2