From 39b5efa5b8fd60f80101cb0f04447a4679097096 Mon Sep 17 00:00:00 2001 From: Daniel Henrique Barboza Date: Mon, 22 Jan 2024 13:10:56 -0300 Subject: [PATCH] target/riscv/csr.c: use 'vlenb' instead of 'vlen' As a bonus, we're being more idiomatic using cpu->cfg.vlenb when reading CSR_VLENB. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-ID: <20240122161107.26737-3-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/csr.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index d666620e48..d9a010387f 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -683,7 +683,7 @@ static RISCVException read_vl(CPURISCVState *env, int csrno, static int read_vlenb(CPURISCVState *env, int csrno, target_ulong *val) { - *val = riscv_cpu_cfg(env)->vlen >> 3; + *val = riscv_cpu_cfg(env)->vlenb; return RISCV_EXCP_NONE; } @@ -738,7 +738,7 @@ static RISCVException write_vstart(CPURISCVState *env, int csrno, * The vstart CSR is defined to have only enough writable bits * to hold the largest element index, i.e. lg2(VLEN) bits. */ - env->vstart = val & ~(~0ULL << ctzl(riscv_cpu_cfg(env)->vlen)); + env->vstart = val & ~(~0ULL << ctzl(riscv_cpu_cfg(env)->vlenb << 3)); return RISCV_EXCP_NONE; } -- 2.30.2