From 3b55ddadef631d8081cb2f73c6c7cb80c634ba2b Mon Sep 17 00:00:00 2001
From: Flora Cui <Flora.Cui@amd.com>
Date: Wed, 2 Dec 2015 09:56:06 +0800
Subject: [PATCH] drm/amdgpu/gfx8: Enable interrupt on ME1_PIPE3
Otherwise FW cannot see the RLC ACK for the memory clean request
It's for Stoney.
Signed-off-by: Flora Cui <Flora.Cui@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 29e02e0fa3d47..6816a1a60a979 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -3756,6 +3756,11 @@ static int gfx_v8_0_cp_compute_resume(struct amdgpu_device *adev)
tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
WREG32(mmCP_HQD_PERSISTENT_STATE, tmp);
mqd->cp_hqd_persistent_state = tmp;
+ if (adev->asic_type == CHIP_STONEY) {
+ tmp = RREG32(mmCP_ME1_PIPE3_INT_CNTL);
+ tmp = REG_SET_FIELD(tmp, CP_ME1_PIPE3_INT_CNTL, GENERIC2_INT_ENABLE, 1);
+ WREG32(mmCP_ME1_PIPE3_INT_CNTL, tmp);
+ }
/* activate the queue */
mqd->cp_hqd_active = 1;
--
2.30.2