From 3cc53c57d0d54b7fc307879443d555c95b466510 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Wed, 20 Jul 2022 12:28:17 +0200 Subject: [PATCH] clk: mediatek: mt8195: Add reset idx for USB/PCIe T-PHY Add the reset idx for the t-phy port 1, used as either USB or PCI-Express (secondary controller) PHY, depending on board-specific configuration/layout. Signed-off-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220720102817.237483-3-angelogioacchino.delregno@collabora.com Signed-off-by: Stephen Boyd --- drivers/clk/mediatek/clk-mt8195-infra_ao.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/mediatek/clk-mt8195-infra_ao.c b/drivers/clk/mediatek/clk-mt8195-infra_ao.c index 75b54ec9c46c9..fcd410461d3bb 100644 --- a/drivers/clk/mediatek/clk-mt8195-infra_ao.c +++ b/drivers/clk/mediatek/clk-mt8195-infra_ao.c @@ -200,6 +200,7 @@ static u16 infra_ao_rst_ofs[] = { static u16 infra_ao_idx_map[] = { [MT8195_INFRA_RST0_THERM_CTRL_SWRST] = 0 * RST_NR_PER_BANK + 0, + [MT8195_INFRA_RST2_USBSIF_P1_SWRST] = 2 * RST_NR_PER_BANK + 18, [MT8195_INFRA_RST2_PCIE_P0_SWRST] = 2 * RST_NR_PER_BANK + 26, [MT8195_INFRA_RST2_PCIE_P1_SWRST] = 2 * RST_NR_PER_BANK + 27, [MT8195_INFRA_RST3_THERM_CTRL_PTP_SWRST] = 3 * RST_NR_PER_BANK + 5, -- 2.30.2