From 43bf2025452d26ba006a7f321daf014cea952c8b Mon Sep 17 00:00:00 2001 From: =?utf8?q?Daniel=20Gonz=C3=A1lez=20Cabanelas?= Date: Fri, 26 Jun 2020 20:39:05 +0200 Subject: [PATCH] ARM: dts: dlink-dns327l: fix reg-init PHY MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit The marvell PHY reg-init registers for the D-Link DNS-327L are wrong. Currently the first field is used to set the page 2, but this is pointless. The usage is not correct, and we are setting the wrong registers. Fix it. Signed-off-by: Daniel González Cabanelas Reviewed-by: Andrew Lunn Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/armada-370-dlink-dns327l.dts | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/armada-370-dlink-dns327l.dts b/arch/arm/boot/dts/armada-370-dlink-dns327l.dts index baa459dd51e44..2008c6eaaa528 100644 --- a/arch/arm/boot/dts/armada-370-dlink-dns327l.dts +++ b/arch/arm/boot/dts/armada-370-dlink-dns327l.dts @@ -247,9 +247,8 @@ &mdio { phy0: ethernet-phy@0 { /* Marvell 88E1318 */ reg = <0>; - marvell,reg-init = <0x0 0x16 0x0 0x0002>, - <0x0 0x19 0x0 0x0077>, - <0x0 0x18 0x0 0x5747>; + marvell,reg-init = <0x2 0x19 0x0 0x0077>, + <0x2 0x18 0x0 0x5747>; }; }; -- 2.30.2