From 48e70d2a1a9c8d58c48b2840feda3aa3bc330a94 Mon Sep 17 00:00:00 2001 From: Matt Roper Date: Thu, 14 Dec 2023 10:47:05 -0800 Subject: [PATCH] drm/xe: Move GSC HECI base offsets out of register header These offsets are only used to setup the auxiliary device BAR information and are never used for driver read/write operations. Move them to the GSC HECI file where they're actually used. Reviewed-by: Lucas De Marchi Link: https://lore.kernel.org/r/20231214184659.2249559-15-matthew.d.roper@intel.com Signed-off-by: Matt Roper Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/xe/regs/xe_regs.h | 4 ---- drivers/gpu/drm/xe/xe_heci_gsc.c | 4 ++++ 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/xe/regs/xe_regs.h b/drivers/gpu/drm/xe/regs/xe_regs.h index b7d3b42ec0031..67ce087e21d08 100644 --- a/drivers/gpu/drm/xe/regs/xe_regs.h +++ b/drivers/gpu/drm/xe/regs/xe_regs.h @@ -7,10 +7,6 @@ #include "regs/xe_reg_defs.h" -#define DG1_GSC_HECI2_BASE 0x00259000 -#define PVC_GSC_HECI2_BASE 0x00285000 -#define DG2_GSC_HECI2_BASE 0x00374000 - #define GT_WAIT_SEMAPHORE_INTERRUPT REG_BIT(11) #define GT_CONTEXT_SWITCH_INTERRUPT REG_BIT(8) #define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT REG_BIT(4) diff --git a/drivers/gpu/drm/xe/xe_heci_gsc.c b/drivers/gpu/drm/xe/xe_heci_gsc.c index d8e982e3d9a2c..19eda00d5cc4e 100644 --- a/drivers/gpu/drm/xe/xe_heci_gsc.c +++ b/drivers/gpu/drm/xe/xe_heci_gsc.c @@ -16,6 +16,10 @@ #define GSC_BAR_LENGTH 0x00000FFC +#define DG1_GSC_HECI2_BASE 0x259000 +#define PVC_GSC_HECI2_BASE 0x285000 +#define DG2_GSC_HECI2_BASE 0x374000 + static void heci_gsc_irq_mask(struct irq_data *d) { /* generic irq handling */ -- 2.30.2