From 4abaa5cc4d7c42ae61ce482acc5aa1e1cededc73 Mon Sep 17 00:00:00 2001 From: Amit Cohen Date: Wed, 29 Jun 2022 12:39:58 +0300 Subject: [PATCH] mlxsw: Align PGT index to legacy bridge model FID code reserves about 15K entries in PGT table for flooding. These entries are just allocated and are not used yet because the code that uses them is skipped now. The next patches will convert MDB code to use PGT APIs. The allocation of indexes for multicast is done after FID code reserves 15K entries. Currently, legacy bridge model is used and firmware manages PGT table. That means that the indexes which are allocated using PGT API are too high when legacy bridge model is used. To not exceed firmware limitation for MDB entries, add an API that returns the correct 'mid_index', based on bridge model. For legacy model, subtract the number of flood entries from PGT index. Use it to write the correct MID to SMID register. This API will be used also from MDB code in the next patches. PGT should not be aware of MDB and FID different usage, this API is temporary and will be removed once unified bridge model will be used. Signed-off-by: Amit Cohen Signed-off-by: Ido Schimmel Signed-off-by: David S. Miller --- drivers/net/ethernet/mellanox/mlxsw/spectrum.h | 1 + .../net/ethernet/mellanox/mlxsw/spectrum_pgt.c | 16 +++++++++++++--- 2 files changed, 14 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlxsw/spectrum.h b/drivers/net/ethernet/mellanox/mlxsw/spectrum.h index b128692611d9a..b7709e7590809 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/spectrum.h +++ b/drivers/net/ethernet/mellanox/mlxsw/spectrum.h @@ -1485,6 +1485,7 @@ void mlxsw_sp_pgt_mid_free_range(struct mlxsw_sp *mlxsw_sp, u16 mid_base, u16 count); int mlxsw_sp_pgt_entry_port_set(struct mlxsw_sp *mlxsw_sp, u16 mid, u16 smpe, u16 local_port, bool member); +u16 mlxsw_sp_pgt_index_to_mid(const struct mlxsw_sp *mlxsw_sp, u16 pgt_index); int mlxsw_sp_pgt_init(struct mlxsw_sp *mlxsw_sp); void mlxsw_sp_pgt_fini(struct mlxsw_sp *mlxsw_sp); diff --git a/drivers/net/ethernet/mellanox/mlxsw/spectrum_pgt.c b/drivers/net/ethernet/mellanox/mlxsw/spectrum_pgt.c index 3b7265b539b27..e6bbe08ef3791 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/spectrum_pgt.c +++ b/drivers/net/ethernet/mellanox/mlxsw/spectrum_pgt.c @@ -182,6 +182,16 @@ static void mlxsw_sp_pgt_entry_put(struct mlxsw_sp_pgt *pgt, u16 mid) mlxsw_sp_pgt_entry_destroy(pgt, pgt_entry); } +#define MLXSW_SP_FID_PGT_FLOOD_ENTRIES 15354 /* Reserved for flooding. */ + +u16 mlxsw_sp_pgt_index_to_mid(const struct mlxsw_sp *mlxsw_sp, u16 pgt_index) +{ + if (mlxsw_sp->ubridge) + return pgt_index; + + return pgt_index - MLXSW_SP_FID_PGT_FLOOD_ENTRIES; +} + static void mlxsw_sp_pgt_smid2_port_set(char *smid2_pl, u16 local_port, bool member) { @@ -196,7 +206,7 @@ mlxsw_sp_pgt_entry_port_write(struct mlxsw_sp *mlxsw_sp, { bool smpe_index_valid; char *smid2_pl; - u16 smpe; + u16 smpe, mid; int err; smid2_pl = kmalloc(MLXSW_REG_SMID2_LEN, GFP_KERNEL); @@ -206,9 +216,9 @@ mlxsw_sp_pgt_entry_port_write(struct mlxsw_sp *mlxsw_sp, smpe_index_valid = mlxsw_sp->ubridge ? mlxsw_sp->pgt->smpe_index_valid : false; smpe = mlxsw_sp->ubridge ? pgt_entry->smpe_index : 0; + mid = mlxsw_sp_pgt_index_to_mid(mlxsw_sp, pgt_entry->index); - mlxsw_reg_smid2_pack(smid2_pl, pgt_entry->index, 0, 0, smpe_index_valid, - smpe); + mlxsw_reg_smid2_pack(smid2_pl, mid, 0, 0, smpe_index_valid, smpe); mlxsw_sp_pgt_smid2_port_set(smid2_pl, local_port, member); err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(smid2), smid2_pl); -- 2.30.2