From 53ba1b2bdaf7f481fdd878e9c18cd0e54081fac9 Mon Sep 17 00:00:00 2001 From: Piyush Mehta Date: Fri, 9 Dec 2022 14:54:47 +0100 Subject: [PATCH] arm64: dts: zynqmp: Add mode-pin GPIO controller DT node Add mode-pin GPIO controller DT node in zynqmp.dtsi and wire it to usb0 controller. All Xilinx evaluation boards are using modepin gpio for ULPI reset that's why wire it directly in zynqmp instead of c&p the same line to every board specific file. Signed-off-by: Piyush Mehta Signed-off-by: Michal Simek Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/69924a8e2c01e5a1d25d098adc53224ddb841f46.1670594085.git.michal.simek@amd.com --- arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index 130df216fa1bb..9793a4e652d94 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -13,6 +13,7 @@ */ #include +#include #include #include @@ -199,6 +200,12 @@ compatible = "xlnx,zynqmp-pinctrl"; status = "disabled"; }; + + modepin_gpio: gpio { + compatible = "xlnx,zynqmp-gpio-modepin"; + gpio-controller; + #gpio-cells = <2>; + }; }; }; @@ -847,6 +854,7 @@ <&zynqmp_reset ZYNQMP_RESET_USB0_HIBERRESET>, <&zynqmp_reset ZYNQMP_RESET_USB0_APB>; reset-names = "usb_crst", "usb_hibrst", "usb_apbrst"; + reset-gpios = <&modepin_gpio 1 GPIO_ACTIVE_LOW>; ranges; dwc3_0: usb@fe200000 { -- 2.30.2