From 59cb29d6a5149871d1acb18fb465879b1af5f3b2 Mon Sep 17 00:00:00 2001 From: Christoph Muellner Date: Fri, 24 Feb 2023 10:25:36 -0300 Subject: [PATCH] target/riscv: add Zicbop cbo.prefetch{i, r, m} placeholder The cmo.prefetch instructions are nops for QEMU (no emulation of the memory hierarchy, no illegal instructions, no permission faults, no traps). Add a comment noting where they would be decoded in case cbo.prefetch instructions become relevant in the future. Co-developed-by: Philipp Tomsich Signed-off-by: Christoph Muellner Signed-off-by: Daniel Henrique Barboza Reviewed-by: Richard Henderson Reviewed-by: Weiwei Li Message-ID: <20230224132536.552293-5-dbarboza@ventanamicro.com> Signed-off-by: Palmer Dabbelt --- target/riscv/insn32.decode | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 282e41aa3e..73d5d1b045 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -134,6 +134,7 @@ addi ............ ..... 000 ..... 0010011 @i slti ............ ..... 010 ..... 0010011 @i sltiu ............ ..... 011 ..... 0010011 @i xori ............ ..... 100 ..... 0010011 @i +# cbo.prefetch_{i,r,m} instructions are ori with rd=x0 and not decoded. ori ............ ..... 110 ..... 0010011 @i andi ............ ..... 111 ..... 0010011 @i slli 00000. ...... ..... 001 ..... 0010011 @sh -- 2.30.2