From 5aaf9079d740ebe57f10dfefb1850011d6bb7b2a Mon Sep 17 00:00:00 2001 From: Biju Das Date: Wed, 15 Mar 2023 06:47:25 +0000 Subject: [PATCH] dt-bindings: dma: rz-dmac: Document clock-names and reset-names Document clock-names and reset-names properties as we have multiple clocks and resets. Signed-off-by: Biju Das Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20230315064726.22739-1-biju.das.jz@bp.renesas.com Signed-off-by: Vinod Koul --- .../devicetree/bindings/dma/renesas,rz-dmac.yaml | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml b/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml index f638d3934e71d..c284abc6784ae 100644 --- a/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml +++ b/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml @@ -54,6 +54,11 @@ properties: - description: DMA main clock - description: DMA register access clock + clock-names: + items: + - const: main + - const: register + '#dma-cells': const: 1 description: @@ -77,16 +82,23 @@ properties: - description: Reset for DMA ARESETN reset terminal - description: Reset for DMA RST_ASYNC reset terminal + reset-names: + items: + - const: arst + - const: rst_async + required: - compatible - reg - interrupts - interrupt-names - clocks + - clock-names - '#dma-cells' - dma-channels - power-domains - resets + - reset-names additionalProperties: false @@ -124,9 +136,11 @@ examples: "ch12", "ch13", "ch14", "ch15"; clocks = <&cpg CPG_MOD R9A07G044_DMAC_ACLK>, <&cpg CPG_MOD R9A07G044_DMAC_PCLK>; + clock-names = "main", "register"; power-domains = <&cpg>; resets = <&cpg R9A07G044_DMAC_ARESETN>, <&cpg R9A07G044_DMAC_RST_ASYNC>; + reset-names = "arst", "rst_async"; #dma-cells = <1>; dma-channels = <16>; }; -- 2.30.2