From 5ef00c06ea5e4e0de1f63d2c620f671750f73f9b Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 16 May 2023 17:45:37 +0200 Subject: [PATCH] arm64: dts: qcom: sm8550: enable DISPCC by default Enable the Display Clock Controller by default in SoC DTSI so unused clocks can be turned off. It does not require any external resources, so as core SoC component should be always available to boards. Suggested-by: Konrad Dybcio Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230516154539.238655-1-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 4 ---- arch/arm64/boot/dts/qcom/sm8550.dtsi | 1 - 2 files changed, 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts index 785889450e8a7..f27d5c657f444 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts @@ -419,10 +419,6 @@ }; }; -&dispcc { - status = "okay"; -}; - &mdss { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 94201d08b5af1..473ab1831ab1b 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -2697,7 +2697,6 @@ #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; - status = "disabled"; }; usb_1_hsphy: phy@88e3000 { -- 2.30.2