From 63ba67ebdfd403ef53aa0fefde3a42e505516e8c Mon Sep 17 00:00:00 2001 From: Atish Patra Date: Mon, 11 Jul 2022 10:46:31 -0700 Subject: [PATCH] RISC-V: Move counter info definition to sbi header file Counter info encoding format is defined by the SBI specificaiton. KVM implementation of SBI PMU extension will also leverage this definition. Move the definition to common sbi header file from the sbi pmu driver. Signed-off-by: Atish Patra Link: https://lore.kernel.org/r/20220711174632.4186047-5-atishp@rivosinc.com Signed-off-by: Palmer Dabbelt --- arch/riscv/include/asm/sbi.h | 14 ++++++++++++++ drivers/perf/riscv_pmu_sbi.c | 14 -------------- 2 files changed, 14 insertions(+), 14 deletions(-) diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index 9e3c2cf1edafe..d633ac0f5a32b 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h @@ -122,6 +122,20 @@ enum sbi_ext_pmu_fid { SBI_EXT_PMU_COUNTER_FW_READ, }; +union sbi_pmu_ctr_info { + unsigned long value; + struct { + unsigned long csr:12; + unsigned long width:6; +#if __riscv_xlen == 32 + unsigned long reserved:13; +#else + unsigned long reserved:45; +#endif + unsigned long type:1; + }; +}; + #define RISCV_PMU_RAW_EVENT_MASK GENMASK_ULL(55, 0) #define RISCV_PMU_RAW_EVENT_IDX 0x20000 diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c index bae614c73b14d..24124546844c1 100644 --- a/drivers/perf/riscv_pmu_sbi.c +++ b/drivers/perf/riscv_pmu_sbi.c @@ -21,20 +21,6 @@ #include #include -union sbi_pmu_ctr_info { - unsigned long value; - struct { - unsigned long csr:12; - unsigned long width:6; -#if __riscv_xlen == 32 - unsigned long reserved:13; -#else - unsigned long reserved:45; -#endif - unsigned long type:1; - }; -}; - /* * RISC-V doesn't have hetergenous harts yet. This need to be part of * per_cpu in case of harts with different pmu counters -- 2.30.2