From 63ce81b224dd8033fd5f629fb4581a26eedd5797 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Fri, 2 Sep 2022 10:11:52 +0200 Subject: [PATCH] arm64: dts: mediatek: cherry: Add Google Security Chip (GSC) TPM Add support for the Cr50 Google Security Chip (GSC) found on this platform on I2C3 to support TPM and to also use it as an entropy source for the kernel. Signed-off-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220902081156.38526-4-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi index 73f531f84fa21..a07e7fe663151 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi @@ -149,6 +149,14 @@ clock-frequency = <400000>; pinctrl-names = "default"; pinctrl-0 = <&i2c3_pins>; + + tpm@50 { + compatible = "google,cr50"; + reg = <0x50>; + interrupts-extended = <&pio 88 IRQ_TYPE_EDGE_FALLING>; + pinctrl-names = "default"; + pinctrl-0 = <&cr50_int>; + }; }; &i2c4 { @@ -426,6 +434,13 @@ "AP_SPI_FLASH_MOSI", "AP_SPI_FLASH_MISO"; + cr50_int: cr50-irq-default-pins { + pins-gsc-ap-int-odl { + pinmux = ; + input-enable; + }; + }; + cros_ec_int: cros-ec-irq-default-pins { pins-ec-ap-int-odl { pinmux = ; -- 2.30.2